mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-21 06:33:41 +00:00
29 lines
1.1 KiB
Diff
29 lines
1.1 KiB
Diff
From 00b0721cce51988b6dda27b21afb0e09c620bc21 Mon Sep 17 00:00:00 2001
|
|
From: John Crispin <blogic@openwrt.org>
|
|
Date: Sat, 27 Oct 2012 09:14:17 +0200
|
|
Subject: [PATCH 107/113] MIPS: lantiq: add xrx200 ethernet clock
|
|
|
|
Signed-off-by: John Crispin <blogic@openwrt.org>
|
|
---
|
|
arch/mips/lantiq/xway/sysctrl.c | 4 ++++
|
|
1 file changed, 4 insertions(+)
|
|
|
|
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
|
|
index 2917b56..3925e66 100644
|
|
--- a/arch/mips/lantiq/xway/sysctrl.c
|
|
+++ b/arch/mips/lantiq/xway/sysctrl.c
|
|
@@ -370,6 +370,10 @@ void __init ltq_soc_init(void)
|
|
clkdev_add_pmu("1d900000.pcie", "pdi", 1, PMU1_PCIE_PDI);
|
|
clkdev_add_pmu("1d900000.pcie", "ctl", 1, PMU1_PCIE_CTL);
|
|
clkdev_add_pmu("1d900000.pcie", "ahb", 0, PMU_AHBM | PMU_AHBS);
|
|
+ clkdev_add_pmu("1e108000.eth", NULL, 0,
|
|
+ PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
|
|
+ PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
|
|
+ PMU_PPE_QSB | PMU_PPE_TOP);
|
|
} else if (of_machine_is_compatible("lantiq,ar9")) {
|
|
clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
|
|
ltq_ar9_fpi_hz());
|
|
--
|
|
1.7.10.4
|
|
|