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b4c02c9998
Removed upstreamed patches:
generic/pending-5.4
445-mtd-spinand-gigadevice-Only-one-dummy-byte-in-QUA.patch
446-mtd-spinand-gigadevice-Add-QE-Bit.patch
pistachio/patches-5.4
150-pwm-img-Fix-null-pointer-access-in-probe.patch
Manually rebased:
layerscape/patches-5.4
801-audio-0011-Revert-ASoC-fsl_sai-add-of_match-data.patch
801-audio-0039-MLK-16224-6-ASoC-fsl_sai-fix-DSD-suspend-resume.patch
801-audio-0073-MLK-21957-3-ASoC-fsl_sai-add-bitcount-and-timestamp-.patch
820-usb-0009-usb-dwc3-Add-workaround-for-host-mode-VBUS-glitch-wh.patch
All modifications made by update_kernel.sh
Build system: x86_64
Build-tested: ipq806x/R7800, ath79/generic, bcm27xx/bcm2711,
mvebu (mamba, rango), x86_64, ramips/mt7621
Run-tested: ipq806x/R7800, mvebu (mamba, rango), x86_64, ramips (RT-AC57U)
No dmesg regressions, everything functional
Signed-off-by: John Audia <graysky@archlinux.us>
[alter 820-usb-0009-usb-dwc3-Add-workaround-for-host-mode-VBUS-glitch-wh]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
47 lines
1.7 KiB
Diff
47 lines
1.7 KiB
Diff
From 1960d75e3251659be8276529e4d01cf6993d9f4a Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Tue, 1 Sep 2020 14:21:44 +0200
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Subject: [PATCH] PCI: qcom: Make sure PCIe is reset before init for rev 2.1.0
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Qsdk U-Boot can incorrectly leave the PCIe interface in an undefined
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state if bootm command is used instead of bootipq. This is caused by the
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not deinit of PCIe when bootm is called. Reset the PCIe before init
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anyway to fix this U-Boot bug.
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
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Cc: stable@vger.kernel.org # v4.19+
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---
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drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++
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1 file changed, 13 insertions(+)
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--- a/drivers/pci/controller/dwc/pcie-qcom.c
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+++ b/drivers/pci/controller/dwc/pcie-qcom.c
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@@ -296,6 +296,9 @@ static void qcom_pcie_deinit_2_1_0(struc
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reset_control_assert(res->por_reset);
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reset_control_assert(res->ext_reset);
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reset_control_assert(res->phy_reset);
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+
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+ writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL);
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+
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regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
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}
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@@ -308,6 +311,16 @@ static int qcom_pcie_init_2_1_0(struct q
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u32 val;
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int ret;
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+ /* reset the PCIe interface as uboot can leave it undefined state */
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+ reset_control_assert(res->pci_reset);
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+ reset_control_assert(res->axi_reset);
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+ reset_control_assert(res->ahb_reset);
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+ reset_control_assert(res->por_reset);
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+ reset_control_assert(res->ext_reset);
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+ reset_control_assert(res->phy_reset);
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+
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+ writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL);
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+
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ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
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if (ret < 0) {
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dev_err(dev, "cannot enable regulators\n");
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