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https://github.com/openwrt/openwrt.git
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4c6fe32468
The QCA953x only supports 25 MHz refclk, however some OEMs set an invalid bootstrap value for the REF_CLK option, which would break the clock detection in ath9k. Force the QCA953x refclk to 25MHz in ath9k, as this is (according to the datasheet) the only valid frequency. Signed-off-by: David Bauer <mail@david-bauer.net>
338 lines
8.1 KiB
Diff
338 lines
8.1 KiB
Diff
--- a/drivers/net/wireless/ath/ath9k/ahb.c
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+++ b/drivers/net/wireless/ath/ath9k/ahb.c
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@@ -20,7 +20,15 @@
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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+#include <linux/of_device.h>
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#include "ath9k.h"
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+#include <linux/ath9k_platform.h>
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+
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+#ifdef CONFIG_OF
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+#include <asm/mach-ath79/ath79.h>
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+#include <asm/mach-ath79/ar71xx_regs.h>
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+#include <linux/mtd/mtd.h>
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+#endif
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static const struct platform_device_id ath9k_platform_id_table[] = {
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{
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@@ -69,6 +77,242 @@ static const struct ath_bus_ops ath_ahb_
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.eeprom_read = ath_ahb_eeprom_read,
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};
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+#ifdef CONFIG_OF
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+
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+#define QCA955X_DDR_CTL_CONFIG 0x108
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+#define QCA955X_DDR_CTL_CONFIG_ACT_WMAC BIT(23)
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+
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+static int of_get_wifi_cal(struct device_node *np, struct ath9k_platform_data *pdata)
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+{
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+#ifdef CONFIG_MTD
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+ struct device_node *mtd_np = NULL;
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+ size_t retlen;
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+ int size, ret;
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+ struct mtd_info *mtd;
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+ const char *part;
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+ const __be32 *list;
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+ phandle phandle;
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+
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+ list = of_get_property(np, "mtd-cal-data", &size);
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+ if (!list)
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+ return 0;
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+
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+ if (size != (2 * sizeof(*list)))
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+ return 1;
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+
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+ phandle = be32_to_cpup(list++);
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+ if (phandle)
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+ mtd_np = of_find_node_by_phandle(phandle);
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+
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+ if (!mtd_np)
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+ return 1;
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+
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+ part = of_get_property(mtd_np, "label", NULL);
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+ if (!part)
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+ part = mtd_np->name;
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+
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+ mtd = get_mtd_device_nm(part);
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+ if (IS_ERR(mtd))
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+ return 1;
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+
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+ ret = mtd_read(mtd, be32_to_cpup(list), sizeof(pdata->eeprom_data),
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+ &retlen, (u8*)pdata->eeprom_data);
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+ put_mtd_device(mtd);
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+
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+#endif
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+ return 0;
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+}
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+
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+static int ar913x_wmac_reset(void)
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+{
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+ ath79_device_reset_set(AR913X_RESET_AMBA2WMAC);
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+ mdelay(10);
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+
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+ ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC);
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+ mdelay(10);
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+
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+ return 0;
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+}
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+
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+static int ar933x_wmac_reset(void)
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+{
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+ int retries = 20;
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+
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+ ath79_device_reset_set(AR933X_RESET_WMAC);
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+ ath79_device_reset_clear(AR933X_RESET_WMAC);
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+
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+ while (1) {
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+ u32 bootstrap;
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+
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+ bootstrap = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
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+ if ((bootstrap & AR933X_BOOTSTRAP_EEPBUSY) == 0)
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+ return 0;
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+
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+ if (retries-- == 0)
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+ break;
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+
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+ udelay(10000);
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+ }
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+
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+ pr_err("ar933x: WMAC reset timed out");
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+ return -ETIMEDOUT;
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+}
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+
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+static int qca955x_wmac_reset(void)
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+{
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+ int i;
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+
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+ /* Try to wait for WMAC DDR activity to stop */
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+ for (i = 0; i < 10; i++) {
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+ if (!(__raw_readl(ath79_ddr_base + QCA955X_DDR_CTL_CONFIG) &
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+ QCA955X_DDR_CTL_CONFIG_ACT_WMAC))
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+ break;
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+
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+ udelay(10);
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+ }
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+
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+ ath79_device_reset_set(QCA955X_RESET_RTC);
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+ udelay(10);
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+ ath79_device_reset_clear(QCA955X_RESET_RTC);
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+ udelay(10);
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+
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+ return 0;
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+}
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+
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+enum {
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+ AR913X_WMAC = 0,
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+ AR933X_WMAC,
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+ AR934X_WMAC,
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+ QCA953X_WMAC,
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+ QCA955X_WMAC,
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+ QCA956X_WMAC,
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+};
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+
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+static int ar9330_get_soc_revision(void)
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+{
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+ if (ath79_soc_rev == 1)
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+ return ath79_soc_rev;
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+
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+ return 0;
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+}
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+
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+static int ath79_get_soc_revision(void)
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+{
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+ return ath79_soc_rev;
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+}
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+
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+static const struct of_ath_ahb_data {
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+ u16 dev_id;
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+ u32 bootstrap_reg;
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+ u32 bootstrap_ref;
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+
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+ int (*soc_revision)(void);
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+ int (*wmac_reset)(void);
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+} of_ath_ahb_data[] = {
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+ [AR913X_WMAC] = {
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+ .dev_id = AR5416_AR9100_DEVID,
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+ .wmac_reset = ar913x_wmac_reset,
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+
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+ },
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+ [AR933X_WMAC] = {
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+ .dev_id = AR9300_DEVID_AR9330,
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+ .bootstrap_reg = AR933X_RESET_REG_BOOTSTRAP,
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+ .bootstrap_ref = AR933X_BOOTSTRAP_REF_CLK_40,
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+ .soc_revision = ar9330_get_soc_revision,
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+ .wmac_reset = ar933x_wmac_reset,
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+ },
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+ [AR934X_WMAC] = {
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+ .dev_id = AR9300_DEVID_AR9340,
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+ .bootstrap_reg = AR934X_RESET_REG_BOOTSTRAP,
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+ .bootstrap_ref = AR934X_BOOTSTRAP_REF_CLK_40,
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+ .soc_revision = ath79_get_soc_revision,
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+ },
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+ [QCA953X_WMAC] = {
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+ .dev_id = AR9300_DEVID_AR953X,
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+ .bootstrap_reg = QCA953X_RESET_REG_BOOTSTRAP,
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+ .bootstrap_ref = QCA953X_BOOTSTRAP_REF_CLK_40,
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+ .soc_revision = ath79_get_soc_revision,
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+ },
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+ [QCA955X_WMAC] = {
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+ .dev_id = AR9300_DEVID_QCA955X,
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+ .bootstrap_reg = QCA955X_RESET_REG_BOOTSTRAP,
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+ .bootstrap_ref = QCA955X_BOOTSTRAP_REF_CLK_40,
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+ .wmac_reset = qca955x_wmac_reset,
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+ },
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+ [QCA956X_WMAC] = {
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+ .dev_id = AR9300_DEVID_QCA956X,
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+ .bootstrap_reg = QCA956X_RESET_REG_BOOTSTRAP,
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+ .bootstrap_ref = QCA956X_BOOTSTRAP_REF_CLK_40,
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+ .soc_revision = ath79_get_soc_revision,
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+ },
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+};
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+
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+const struct of_device_id of_ath_ahb_match[] = {
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+ { .compatible = "qca,ar9130-wmac", .data = &of_ath_ahb_data[AR913X_WMAC] },
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+ { .compatible = "qca,ar9330-wmac", .data = &of_ath_ahb_data[AR933X_WMAC] },
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+ { .compatible = "qca,ar9340-wmac", .data = &of_ath_ahb_data[AR934X_WMAC] },
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+ { .compatible = "qca,qca9530-wmac", .data = &of_ath_ahb_data[QCA953X_WMAC] },
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+ { .compatible = "qca,qca9550-wmac", .data = &of_ath_ahb_data[QCA955X_WMAC] },
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+ { .compatible = "qca,qca9560-wmac", .data = &of_ath_ahb_data[QCA956X_WMAC] },
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+ {},
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+};
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+MODULE_DEVICE_TABLE(of, of_ath_ahb_match);
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+
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+static int of_ath_ahb_probe(struct platform_device *pdev)
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+{
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+ struct ath9k_platform_data *pdata;
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+ const struct of_device_id *match;
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+ const struct of_ath_ahb_data *data;
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+ u8 led_pin;
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+
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+ match = of_match_device(of_ath_ahb_match, &pdev->dev);
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+ data = (const struct of_ath_ahb_data *)match->data;
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+
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+ pdata = dev_get_platdata(&pdev->dev);
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+
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+ if (!of_property_read_u8(pdev->dev.of_node, "qca,led-pin", &led_pin))
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+ pdata->led_pin = led_pin;
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+ else
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+ pdata->led_pin = -1;
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+
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+ if (of_property_read_bool(pdev->dev.of_node, "qca,disable-2ghz"))
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+ pdata->disable_2ghz = true;
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+
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+ if (of_property_read_bool(pdev->dev.of_node, "qca,disable-5ghz"))
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+ pdata->disable_5ghz = true;
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+
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+ if (of_property_read_bool(pdev->dev.of_node, "qca,tx-gain-buffalo"))
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+ pdata->tx_gain_buffalo = true;
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+
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+ if (data->wmac_reset) {
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+ data->wmac_reset();
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+ pdata->external_reset = data->wmac_reset;
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+ }
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+
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+ if (data->dev_id == AR9300_DEVID_AR953X) {
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+ /*
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+ * QCA953x only supports 25MHz refclk.
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+ * Some vendors have an invalid bootstrap option
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+ * set, which would break the WMAC here.
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+ */
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+ pdata->is_clk_25mhz = true;
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+ } else if (data->bootstrap_reg && data->bootstrap_ref) {
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+ u32 t = ath79_reset_rr(data->bootstrap_reg);
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+ if (t & data->bootstrap_ref)
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+ pdata->is_clk_25mhz = false;
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+ else
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+ pdata->is_clk_25mhz = true;
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+ }
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+
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+ pdata->get_mac_revision = data->soc_revision;
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+
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+ if (of_get_wifi_cal(pdev->dev.of_node, pdata))
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+ dev_err(&pdev->dev, "failed to load calibration data from mtd device\n");
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+
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+ return data->dev_id;
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+}
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+#endif
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+
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static int ath_ahb_probe(struct platform_device *pdev)
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{
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void __iomem *mem;
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@@ -80,6 +324,17 @@ static int ath_ahb_probe(struct platform
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int ret = 0;
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struct ath_hw *ah;
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char hw_name[64];
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+ u16 dev_id;
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+
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+ if (id)
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+ dev_id = id->driver_data;
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+
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+#ifdef CONFIG_OF
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+ if (pdev->dev.of_node)
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+ pdev->dev.platform_data = devm_kzalloc(&pdev->dev,
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+ sizeof(struct ath9k_platform_data),
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+ GFP_KERNEL);
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+#endif
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if (!dev_get_platdata(&pdev->dev)) {
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dev_err(&pdev->dev, "no platform data specified\n");
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@@ -122,13 +377,16 @@ static int ath_ahb_probe(struct platform
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sc->mem = mem;
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sc->irq = irq;
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+#ifdef CONFIG_OF
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+ dev_id = of_ath_ahb_probe(pdev);
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+#endif
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ret = request_irq(irq, ath_isr, IRQF_SHARED, "ath9k", sc);
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if (ret) {
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dev_err(&pdev->dev, "request_irq failed\n");
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goto err_free_hw;
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}
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- ret = ath9k_init_device(id->driver_data, sc, &ath_ahb_bus_ops);
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+ ret = ath9k_init_device(dev_id, sc, &ath_ahb_bus_ops);
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if (ret) {
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dev_err(&pdev->dev, "failed to initialize device\n");
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goto err_irq;
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@@ -159,6 +417,9 @@ static int ath_ahb_remove(struct platfor
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free_irq(sc->irq, sc);
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ieee80211_free_hw(sc->hw);
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}
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+#ifdef CONFIG_OF
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+ pdev->dev.platform_data = NULL;
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+#endif
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return 0;
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}
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@@ -168,6 +429,9 @@ static struct platform_driver ath_ahb_dr
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.remove = ath_ahb_remove,
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.driver = {
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.name = "ath9k",
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+#ifdef CONFIG_OF
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+ .of_match_table = of_ath_ahb_match,
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+#endif
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},
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.id_table = ath9k_platform_id_table,
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};
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--- a/drivers/net/wireless/ath/ath9k/ath9k.h
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+++ b/drivers/net/wireless/ath/ath9k/ath9k.h
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@@ -25,6 +25,7 @@
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#include <linux/time.h>
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#include <linux/hw_random.h>
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#include <linux/gpio/driver.h>
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+#include <linux/reset.h>
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#include "common.h"
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#include "debug.h"
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@@ -1011,6 +1012,9 @@ struct ath_softc {
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struct ath_hw *sc_ah;
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void __iomem *mem;
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int irq;
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+#ifdef CONFIG_OF
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+ struct reset_control *reset;
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+#endif
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spinlock_t sc_serial_rw;
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spinlock_t sc_pm_lock;
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spinlock_t sc_pcu_lock;
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