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211 lines
7.0 KiB
Diff
211 lines
7.0 KiB
Diff
From 69f3f8c51077d0f3dc7f46c2c9a94da899d8eb7c Mon Sep 17 00:00:00 2001
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From: Annaliese McDermond <nh6z@nh6z.net>
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Date: Thu, 21 Mar 2019 17:58:48 -0700
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Subject: [PATCH 402/806] ASoC: tlv320aic32x4: Model BDIV divider in CCF
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commit 9b484124ebd906c4d6bc826cc0d417e80cc1105c upstream.
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Model and manage BDIV divider as components in the Core
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Clock Framework. This should allow us to do some more complex
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clock management and power control. Also, some of the
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on-board chip clocks can be exposed to the outside, and this
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change will make those clocks easier to consume by other
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parts of the kernel.
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Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
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Signed-off-by: Mark Brown <broonie@kernel.org>
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---
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sound/soc/codecs/tlv320aic32x4-clk.c | 36 ++++++++++++++++++
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sound/soc/codecs/tlv320aic32x4.c | 56 +++++++++++++---------------
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2 files changed, 62 insertions(+), 30 deletions(-)
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--- a/sound/soc/codecs/tlv320aic32x4-clk.c
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+++ b/sound/soc/codecs/tlv320aic32x4-clk.c
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@@ -351,6 +351,34 @@ static const struct clk_ops aic32x4_div_
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.recalc_rate = clk_aic32x4_div_recalc_rate,
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};
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+static int clk_aic32x4_bdiv_set_parent(struct clk_hw *hw, u8 index)
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+{
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+ struct clk_aic32x4 *mux = to_clk_aic32x4(hw);
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+
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+ return regmap_update_bits(mux->regmap, AIC32X4_IFACE3,
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+ AIC32X4_BDIVCLK_MASK, index);
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+}
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+
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+static u8 clk_aic32x4_bdiv_get_parent(struct clk_hw *hw)
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+{
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+ struct clk_aic32x4 *mux = to_clk_aic32x4(hw);
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+ unsigned int val;
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+
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+ regmap_read(mux->regmap, AIC32X4_IFACE3, &val);
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+
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+ return val & AIC32X4_BDIVCLK_MASK;
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+}
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+
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+static const struct clk_ops aic32x4_bdiv_ops = {
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+ .prepare = clk_aic32x4_div_prepare,
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+ .unprepare = clk_aic32x4_div_unprepare,
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+ .set_parent = clk_aic32x4_bdiv_set_parent,
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+ .get_parent = clk_aic32x4_bdiv_get_parent,
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+ .set_rate = clk_aic32x4_div_set_rate,
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+ .round_rate = clk_aic32x4_div_round_rate,
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+ .recalc_rate = clk_aic32x4_div_recalc_rate,
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+};
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+
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static struct aic32x4_clkdesc aic32x4_clkdesc_array[] = {
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{
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.name = "pll",
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@@ -396,6 +424,14 @@ static struct aic32x4_clkdesc aic32x4_cl
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.ops = &aic32x4_div_ops,
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.reg = AIC32X4_MADC,
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},
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+ {
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+ .name = "bdiv",
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+ .parent_names =
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+ (const char *[]) { "ndac", "mdac", "nadc", "madc" },
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+ .num_parents = 4,
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+ .ops = &aic32x4_bdiv_ops,
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+ .reg = AIC32X4_BCLKN,
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+ },
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};
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static struct clk *aic32x4_register_clk(struct device *dev,
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--- a/sound/soc/codecs/tlv320aic32x4.c
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+++ b/sound/soc/codecs/tlv320aic32x4.c
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@@ -57,7 +57,7 @@ struct aic32x4_rate_divs {
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u8 aosr;
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unsigned long nadc_rate;
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unsigned long madc_rate;
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- u8 blck_N;
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+ unsigned long bdiv_rate;
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u8 r_block;
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u8 p_block;
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};
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@@ -310,53 +310,53 @@ static const struct snd_kcontrol_new aic
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static const struct aic32x4_rate_divs aic32x4_divs[] = {
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/* 8k rate */
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{ 12000000, 8000, 57120000, 768, 18432000, 6144000, 128, 18432000,
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- 1024000, 24, 1, 1 },
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+ 1024000, 256000, 1, 1 },
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{ 24000000, 8000, 57120000, 768, 6144000, 6144000, 64, 2048000,
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- 512000, 24, 1, 1 },
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+ 512000, 256000, 1, 1 },
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{ 25000000, 8000, 32620000, 768, 6144000, 6144000, 64, 2048000,
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- 512000, 24, 1, 1 },
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+ 512000, 256000, 1, 1 },
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/* 11.025k rate */
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{ 12000000, 11025, 44217600, 512, 11289600, 5644800, 128, 11289600,
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- 1411200, 16, 1, 1 },
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+ 1411200, 352800, 1, 1 },
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{ 24000000, 11025, 44217600, 512, 5644800, 5644800, 64, 2822400,
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- 705600, 16, 1, 1 },
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+ 705600, 352800, 1, 1 },
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/* 16k rate */
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{ 12000000, 16000, 57120000, 384, 18432000, 6144000, 128, 18432000,
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- 2048000, 12, 1, 1 },
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+ 2048000, 512000, 1, 1 },
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{ 24000000, 16000, 57120000, 384, 6144000, 6144000, 64, 5120000,
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- 1024000, 12, 1, 1 },
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+ 1024000, 512000, 1, 1 },
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{ 25000000, 16000, 32620000, 384, 6144000, 6144000, 64, 5120000,
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- 1024000, 12, 1, 1 },
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+ 1024000, 512000, 1, 1 },
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/* 22.05k rate */
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{ 12000000, 22050, 44217600, 256, 22579200, 5644800, 128, 22579200,
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- 2822400, 8, 1, 1 },
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+ 2822400, 705600, 1, 1 },
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{ 24000000, 22050, 44217600, 256, 5644800, 5644800, 64, 5644800,
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- 1411200, 8, 1, 1 },
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+ 1411200, 705600, 1, 1 },
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{ 25000000, 22050, 19713750, 256, 5644800, 5644800, 64, 5644800,
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- 1411200, 8, 1, 1 },
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+ 1411200, 705600, 1, 1 },
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/* 32k rate */
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{ 12000000, 32000, 14112000, 192, 43008000, 6144000, 64, 43008000,
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- 2048000, 6, 1, 1 },
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+ 2048000, 1024000, 1, 1 },
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{ 24000000, 32000, 14112000, 192, 12288000, 6144000, 64, 12288000,
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- 2048000, 6, 1, 1 },
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+ 2048000, 1024000, 1, 1 },
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/* 44.1k rate */
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{ 12000000, 44100, 44217600, 128, 45158400, 5644800, 128, 45158400,
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- 5644800, 4, 1, 1 },
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+ 5644800, 1411200, 1, 1 },
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{ 24000000, 44100, 44217600, 128, 11289600, 5644800, 64, 11289600,
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- 2822400, 4, 1, 1 },
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+ 2822400, 1411200, 1, 1 },
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{ 25000000, 44100, 19713750, 128, 11289600, 5644800, 64, 11289600,
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- 2822400, 4, 1, 1 },
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+ 2822400, 1411200, 1, 1 },
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/* 48k rate */
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{ 12000000, 48000, 18432000, 128, 49152000, 6144000, 128, 49152000,
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- 6144000, 4, 1, 1 },
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+ 6144000, 1536000, 1, 1 },
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{ 24000000, 48000, 18432000, 128, 12288000, 6144000, 64, 12288000,
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- 3072000, 4, 1, 1 },
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+ 3072000, 1536000, 1, 1 },
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{ 25000000, 48000, 75626250, 128, 12288000, 6144000, 64, 12288000,
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- 3072000, 4, 1, 1 },
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+ 3072000, 1536000, 1, 1 },
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/* 96k rate */
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{ 25000000, 96000, 75626250, 64, 24576000, 6144000, 64, 24576000,
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- 6144000, 1, 1, 9 },
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+ 6144000, 3072000, 1, 9 },
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};
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static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
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@@ -745,6 +745,7 @@ static int aic32x4_setup_clocks(struct s
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{ .id = "madc" },
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{ .id = "ndac" },
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{ .id = "mdac" },
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+ { .id = "bdiv" },
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};
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i = aic32x4_get_divs(parent_rate, sample_rate);
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@@ -762,14 +763,10 @@ static int aic32x4_setup_clocks(struct s
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clk_set_rate(clocks[2].clk, aic32x4_divs[i].madc_rate);
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clk_set_rate(clocks[3].clk, aic32x4_divs[i].ndac_rate);
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clk_set_rate(clocks[4].clk, aic32x4_divs[i].mdac_rate);
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+ clk_set_rate(clocks[5].clk, aic32x4_divs[i].bdiv_rate);
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aic32x4_set_processing_blocks(component, aic32x4_divs[i].r_block, aic32x4_divs[i].p_block);
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- /* DAC_MOD_CLK as BDIV_CLKIN */
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- snd_soc_component_update_bits(component, AIC32X4_IFACE3,
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- AIC32X4_BDIVCLK_MASK,
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- AIC32X4_DACMOD2BCLK << AIC32X4_BDIVCLK_SHIFT);
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-
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/* DOSR MSB & LSB values */
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snd_soc_component_write(component, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8);
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snd_soc_component_write(component, AIC32X4_DOSRLSB, (aic32x4_divs[i].dosr & 0xff));
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@@ -777,10 +774,6 @@ static int aic32x4_setup_clocks(struct s
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/* AOSR value */
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snd_soc_component_write(component, AIC32X4_AOSR, aic32x4_divs[i].aosr);
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- /* BCLK N divider */
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- snd_soc_component_update_bits(component, AIC32X4_BCLKN,
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- AIC32X4_BCLK_MASK, aic32x4_divs[i].blck_N);
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-
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return 0;
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}
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@@ -1003,6 +996,8 @@ static int aic32x4_component_probe(struc
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struct clk_bulk_data clocks[] = {
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{ .id = "codec_clkin" },
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{ .id = "pll" },
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+ { .id = "bdiv" },
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+ { .id = "mdac" },
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};
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ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
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@@ -1020,6 +1015,7 @@ static int aic32x4_component_probe(struc
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aic32x4_setup_gpios(component);
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clk_set_parent(clocks[0].clk, clocks[1].clk);
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+ clk_set_parent(clocks[2].clk, clocks[3].clk);
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/* Power platform configuration */
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if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
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