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124 lines
3.5 KiB
Diff
124 lines
3.5 KiB
Diff
From 5971a2f283d21eab36d7de24d35301f081f83418 Mon Sep 17 00:00:00 2001
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From: Reinder de Haan <patchesrdh@mveas.com>
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Date: Tue, 3 Nov 2015 15:14:20 +0100
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Subject: [PATCH] ARM: dts: sun8i: Add usbphy and usb host controller nodes
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Add nodes describing the H3's usbphy and usb host controller nodes.
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Signed-off-by: Reinder de Haan <patchesrdh@mveas.com>
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Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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---
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arch/arm/boot/dts/sun8i-h3.dtsi | 101 ++++++++++++++++++++++++++++++++++++++++
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1 file changed, 101 insertions(+)
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--- a/arch/arm/boot/dts/sun8i-h3.dtsi
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+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
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@@ -362,6 +362,107 @@
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#size-cells = <0>;
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};
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+ usbphy: phy@01c19400 {
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+ compatible = "allwinner,sun8i-h3-usb-phy";
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+ reg = <0x01c19400 0x2c>,
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+ <0x01c1a800 0x4>,
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+ <0x01c1b800 0x4>,
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+ <0x01c1c800 0x4>,
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+ <0x01c1d800 0x4>;
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+ reg-names = "phy_ctrl",
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+ "pmu0",
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+ "pmu1",
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+ "pmu2",
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+ "pmu3";
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+ clocks = <&usb_clk 8>,
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+ <&usb_clk 9>,
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+ <&usb_clk 10>,
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+ <&usb_clk 11>;
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+ clock-names = "usb0_phy",
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+ "usb1_phy",
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+ "usb2_phy",
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+ "usb3_phy";
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+ resets = <&usb_clk 0>,
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+ <&usb_clk 1>,
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+ <&usb_clk 2>,
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+ <&usb_clk 3>;
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+ reset-names = "usb0_reset",
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+ "usb1_reset",
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+ "usb2_reset",
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+ "usb3_reset";
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+ status = "disabled";
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+ #phy-cells = <1>;
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+ };
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+
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+ ehci1: usb@01c1b000 {
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+ compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
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+ reg = <0x01c1b000 0x100>;
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+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&bus_gates 25>, <&bus_gates 29>;
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+ resets = <&ahb_rst 25>, <&ahb_rst 29>;
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+ phys = <&usbphy 1>;
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+ phy-names = "usb";
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+ status = "disabled";
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+ };
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+
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+ ohci1: usb@01c1b400 {
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+ compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
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+ reg = <0x01c1b400 0x100>;
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+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&bus_gates 29>, <&bus_gates 25>,
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+ <&usb_clk 17>;
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+ resets = <&ahb_rst 29>, <&ahb_rst 25>;
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+ phys = <&usbphy 1>;
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+ phy-names = "usb";
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+ status = "disabled";
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+ };
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+
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+ ehci2: usb@01c1c000 {
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+ compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
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+ reg = <0x01c1c000 0x100>;
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+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&bus_gates 26>, <&bus_gates 30>;
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+ resets = <&ahb_rst 26>, <&ahb_rst 30>;
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+ phys = <&usbphy 2>;
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+ phy-names = "usb";
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+ status = "disabled";
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+ };
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+
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+ ohci2: usb@01c1c400 {
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+ compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
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+ reg = <0x01c1c400 0x100>;
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+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&bus_gates 30>, <&bus_gates 26>,
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+ <&usb_clk 18>;
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+ resets = <&ahb_rst 30>, <&ahb_rst 26>;
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+ phys = <&usbphy 2>;
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+ phy-names = "usb";
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+ status = "disabled";
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+ };
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+
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+ ehci3: usb@01c1d000 {
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+ compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
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+ reg = <0x01c1d000 0x100>;
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+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&bus_gates 27>, <&bus_gates 31>;
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+ resets = <&ahb_rst 27>, <&ahb_rst 31>;
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+ phys = <&usbphy 3>;
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+ phy-names = "usb";
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+ status = "disabled";
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+ };
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+
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+ ohci3: usb@01c1d400 {
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+ compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
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+ reg = <0x01c1d400 0x100>;
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+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&bus_gates 31>, <&bus_gates 27>,
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+ <&usb_clk 19>;
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+ resets = <&ahb_rst 31>, <&ahb_rst 27>;
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+ phys = <&usbphy 3>;
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+ phy-names = "usb";
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+ status = "disabled";
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+ };
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+
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pio: pinctrl@01c20800 {
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compatible = "allwinner,sun8i-h3-pinctrl";
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reg = <0x01c20800 0x400>;
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