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2777947a75
Refreshed all patches. Compile-tested on: cns3xxx Runtime-tested on: cns3xxx Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
187 lines
7.0 KiB
Diff
187 lines
7.0 KiB
Diff
From e7759c44e0c20dd6b5a259300acdc7350ea6dd32 Mon Sep 17 00:00:00 2001
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From: Linus Walleij <linus.walleij@linaro.org>
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Date: Mon, 6 Nov 2017 21:27:34 +0100
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Subject: [PATCH 07/31] pinctrl: gemini: Fix GMAC groups
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The GMII groups need to be split across GMAC0 and GMAC1 since
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GMAC0 is always available but GMAC1 masks GPIO2 lines 0-7
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so we might want just one interface out.
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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---
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drivers/pinctrl/pinctrl-gemini.c | 79 +++++++++++++++++++++++++++-------------
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1 file changed, 54 insertions(+), 25 deletions(-)
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--- a/drivers/pinctrl/pinctrl-gemini.c
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+++ b/drivers/pinctrl/pinctrl-gemini.c
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@@ -96,6 +96,13 @@ struct gemini_pin_group {
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* you are stuck with it.
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*/
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#define GLOBAL_MISC_CTRL 0x30
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+#define GEMINI_GMAC_IOSEL_MASK GENMASK(28, 27)
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+/* Not really used */
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+#define GEMINI_GMAC_IOSEL_GMAC0_GMII BIT(28)
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+/* Activated with GMAC1 */
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+#define GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII BIT(27)
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+/* This will be the default */
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+#define GEMINI_GMAC_IOSEL_GMAC0_RGMII_GMAC1_GPIO2 0
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#define TVC_CLK_PAD_ENABLE BIT(20)
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#define PCI_CLK_PAD_ENABLE BIT(17)
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#define LPC_CLK_PAD_ENABLE BIT(16)
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@@ -109,8 +116,8 @@ struct gemini_pin_group {
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#define NAND_PADS_DISABLE BIT(2)
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#define PFLASH_PADS_DISABLE BIT(1)
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#define SFLASH_PADS_DISABLE BIT(0)
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-#define PADS_MASK (GENMASK(9, 0) | BIT(16) | BIT(17) | BIT(20))
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-#define PADS_MAXBIT 20
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+#define PADS_MASK (GENMASK(9, 0) | BIT(16) | BIT(17) | BIT(20) | BIT(27))
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+#define PADS_MAXBIT 27
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/* Ordered by bit index */
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static const char * const gemini_padgroups[] = {
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@@ -516,9 +523,12 @@ static const unsigned int usb_3512_pins[
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};
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/* GMII, ethernet pins */
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-static const unsigned int gmii_3512_pins[] = {
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- 311, 240, 258, 276, 294, 312, 241, 259, 277, 295, 313, 242, 260, 278, 296,
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- 315, 297, 279, 261, 243, 316, 298, 280, 262, 244, 317, 299, 281
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+static const unsigned int gmii_gmac0_3512_pins[] = {
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+ 240, 241, 242, 258, 259, 260, 276, 277, 278, 294, 295, 311, 312, 313
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+};
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+
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+static const unsigned int gmii_gmac1_3512_pins[] = {
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+ 243, 244, 261, 262, 279, 280, 281, 296, 297, 298, 299, 315, 316, 317
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};
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static const unsigned int pci_3512_pins[] = {
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@@ -671,10 +681,10 @@ static const unsigned int gpio1c_3512_pi
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/* The GPIO1D (28-31) pins overlap with LCD and TVC */
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static const unsigned int gpio1d_3512_pins[] = { 246, 319, 301, 283 };
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-/* The GPIO2A (0-3) pins overlap with GMII and extended parallel flash */
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+/* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */
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static const unsigned int gpio2a_3512_pins[] = { 315, 297, 279, 261 };
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-/* The GPIO2B (4-7) pins overlap with GMII, extended parallel flash and LCD */
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+/* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */
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static const unsigned int gpio2b_3512_pins[] = { 262, 244, 317, 299 };
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/* The GPIO2C (8-31) pins overlap with PCI */
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@@ -741,9 +751,16 @@ static const struct gemini_pin_group gem
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.num_pins = ARRAY_SIZE(usb_3512_pins),
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},
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{
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- .name = "gmiigrp",
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- .pins = gmii_3512_pins,
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- .num_pins = ARRAY_SIZE(gmii_3512_pins),
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+ .name = "gmii_gmac0_grp",
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+ .pins = gmii_gmac0_3512_pins,
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+ .num_pins = ARRAY_SIZE(gmii_gmac0_3512_pins),
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+ },
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+ {
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+ .name = "gmii_gmac1_grp",
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+ .pins = gmii_gmac1_3512_pins,
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+ .num_pins = ARRAY_SIZE(gmii_gmac1_3512_pins),
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+ /* Bring out RGMII on the GMAC1 pins */
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+ .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
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},
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{
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.name = "pcigrp",
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@@ -963,14 +980,15 @@ static const struct gemini_pin_group gem
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.name = "gpio2agrp",
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.pins = gpio2a_3512_pins,
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.num_pins = ARRAY_SIZE(gpio2a_3512_pins),
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- /* Conflict with GMII and extended parallel flash */
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+ .mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
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+ /* Conflict with GMII GMAC1 and extended parallel flash */
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},
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{
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.name = "gpio2bgrp",
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.pins = gpio2b_3512_pins,
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.num_pins = ARRAY_SIZE(gpio2b_3512_pins),
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- /* Conflict with GMII, extended parallel flash and LCD */
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- .mask = LCD_PADS_ENABLE,
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+ /* Conflict with GMII GMAC1, extended parallel flash and LCD */
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+ .mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
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},
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{
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.name = "gpio2cgrp",
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@@ -1450,9 +1468,12 @@ static const unsigned int usb_3516_pins[
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};
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/* GMII, ethernet pins */
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-static const unsigned int gmii_3516_pins[] = {
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- 306, 307, 308, 309, 310, 325, 326, 327, 328, 329, 330, 345, 346, 347,
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- 348, 349, 350, 351, 367, 368, 369, 370, 371, 386, 387, 389, 390, 391
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+static const unsigned int gmii_gmac0_3516_pins[] = {
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+ 306, 307, 325, 326, 327, 328, 345, 346, 347, 348, 367, 368, 386, 387
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+};
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+
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+static const unsigned int gmii_gmac1_3516_pins[] = {
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+ 308, 309, 310, 329, 330, 349, 350, 351, 369, 370, 371, 389, 390, 391
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};
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static const unsigned int pci_3516_pins[] = {
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@@ -1600,10 +1621,10 @@ static const unsigned int gpio1c_3516_pi
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/* The GPIO1D (28-31) pins overlap with TVC */
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static const unsigned int gpio1d_3516_pins[] = { 353, 311, 394, 374 };
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-/* The GPIO2A (0-3) pins overlap with GMII and extended parallel flash */
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+/* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */
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static const unsigned int gpio2a_3516_pins[] = { 308, 369, 389, 329 };
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-/* The GPIO2B (4-7) pins overlap with GMII, extended parallel flash and LCD */
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+/* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */
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static const unsigned int gpio2b_3516_pins[] = { 391, 351, 310, 371 };
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/* The GPIO2C (8-31) pins overlap with PCI */
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@@ -1675,9 +1696,16 @@ static const struct gemini_pin_group gem
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.num_pins = ARRAY_SIZE(usb_3516_pins),
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},
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{
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- .name = "gmiigrp",
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- .pins = gmii_3516_pins,
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- .num_pins = ARRAY_SIZE(gmii_3516_pins),
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+ .name = "gmii_gmac0_grp",
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+ .pins = gmii_gmac0_3516_pins,
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+ .num_pins = ARRAY_SIZE(gmii_gmac0_3516_pins),
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+ },
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+ {
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+ .name = "gmii_gmac1_grp",
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+ .pins = gmii_gmac1_3516_pins,
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+ .num_pins = ARRAY_SIZE(gmii_gmac1_3516_pins),
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+ /* Bring out RGMII on the GMAC1 pins */
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+ .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
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},
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{
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.name = "pcigrp",
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@@ -1889,14 +1917,15 @@ static const struct gemini_pin_group gem
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.name = "gpio2agrp",
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.pins = gpio2a_3516_pins,
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.num_pins = ARRAY_SIZE(gpio2a_3516_pins),
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- /* Conflict with GMII and extended parallel flash */
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+ .mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
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+ /* Conflict with GMII GMAC1 and extended parallel flash */
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},
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{
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.name = "gpio2bgrp",
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.pins = gpio2b_3516_pins,
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.num_pins = ARRAY_SIZE(gpio2b_3516_pins),
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- /* Conflict with GMII, extended parallel flash and LCD */
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- .mask = LCD_PADS_ENABLE,
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+ /* Conflict with GMII GMAC1, extended parallel flash and LCD */
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+ .mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
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},
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{
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.name = "gpio2cgrp",
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@@ -1999,7 +2028,7 @@ static const char * const icegrps[] = {
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static const char * const idegrps[] = { "idegrp" };
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static const char * const satagrps[] = { "satagrp" };
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static const char * const usbgrps[] = { "usbgrp" };
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-static const char * const gmiigrps[] = { "gmiigrp" };
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+static const char * const gmiigrps[] = { "gmii_gmac0_grp", "gmii_gmac1_grp" };
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static const char * const pcigrps[] = { "pcigrp" };
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static const char * const lpcgrps[] = { "lpcgrp" };
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static const char * const lcdgrps[] = { "lcdgrp" };
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