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7bba7ccde9
The root overlay is mounted on the "rootfs_data" partition. This comes at the end of the firmware image, courtesy of mtdsplit. There is very little space left (About 1MB), which can fill up rapidly. The "firmware" and "firmware2" partitions are part of the bootloader dual firmware logic. They should contain independent, valid uImages. This leaves "jffs2-cfg" (mtd3) and "jffs2-log" (mtd4) as candidates. mtd3 is about 13.7 MB and is used by the vendor firmware to store configuration settings. It is only erased by vendor firmware during a factory reset. By naming this partition "rootfs_data", it becomes the root overlay, providing significantly more room. Even with mtdsplit wanting to create a "rootfs_data" on the firmware partition, mtd3 is used as the overlay. Rename "jffs2-cfg" to "rootfs_data", and profit from the extra space. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
230 lines
4.2 KiB
Plaintext
230 lines
4.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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#include "rtl838x.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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compatible = "engenius,ews2910p", "realtek,rtl838x-soc";
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model = "EnGenius EWS2910P";
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aliases {
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led-boot = &led_power;
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led-failsafe = &led_fault;
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led-running = &led_power;
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led-upgrade = &led_power;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x10000000>;
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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led_mode {
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label = "led-mode";
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gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
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linux,code = <BTN_0>;
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};
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};
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gpio1: rtl8231-gpio {
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compatible = "realtek,rtl8231-gpio";
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#gpio-cells = <2>;
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gpio-controller;
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indirect-access-bus-id = <0>;
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poe_enable {
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gpio-hog;
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gpios = <1 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "poe-enable";
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};
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sff_p9_gpios {
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gpio-hog;
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gpios = < 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>,
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< 11 GPIO_ACTIVE_HIGH>, /* los-gpio */
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< 12 GPIO_ACTIVE_LOW>; /* mod-def0-gpio */
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input;
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line-name = "sff-p9-gpios";
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};
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};
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gpio-export {
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compatible = "gpio-export";
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sff-p9-tx-disable {
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gpio-export,name = "sff-p9-tx-disable";
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gpio-export,output = <1>;
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gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
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};
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};
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gpio-restart {
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compatible = "gpio-restart";
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gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
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};
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leds {
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compatible = "gpio-leds";
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led_power: led-0 {
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label = "green:power";
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gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
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};
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led_lan_mode: led-1 {
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label = "green:lan-mode";
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gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
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};
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led_fault: led-2 {
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label = "amber:fault";
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gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
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};
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led_poe_max: led-3 {
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label = "amber:poe-max";
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gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
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};
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};
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i2c1: i2c-gpio-1 {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio1 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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sfp1: sfp-p10 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c1>;
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tx-disable-gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
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los-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio1 21 GPIO_ACTIVE_LOW>;
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x80000>;
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read-only;
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};
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partition@80000 {
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label = "u-boot-env";
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reg = <0x80000 0x10000>;
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read-only;
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};
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partition@90000 {
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label = "u-boot-env2";
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reg = <0x90000 0x10000>;
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};
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partition@a0000 {
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label = "rootfs_data";
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reg = <0xa0000 0xd60000>;
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};
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partition@e00000 {
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label = "jffs2-log";
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reg = <0xe00000 0x200000>;
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};
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partition@1000000 {
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compatible = "openwrt,uimage";
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label = "firmware";
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reg = <0x1000000 0x800000>;
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openwrt,ih-magic = <0x03802910>;
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};
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partition@1800000 {
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label = "firmware2";
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reg = <0x1800000 0x800000>;
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};
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};
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};
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};
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ðernet0 {
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mdio: mdio-bus {
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compatible = "realtek,rtl838x-mdio";
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regmap = <ðernet0>;
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#address-cells = <1>;
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#size-cells = <0>;
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INTERNAL_PHY(8)
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INTERNAL_PHY(9)
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INTERNAL_PHY(10)
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INTERNAL_PHY(11)
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INTERNAL_PHY(12)
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INTERNAL_PHY(13)
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INTERNAL_PHY(14)
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INTERNAL_PHY(15)
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INTERNAL_PHY(24)
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INTERNAL_PHY(26)
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};
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};
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&switch0 {
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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SWITCH_PORT(8, 1, internal)
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SWITCH_PORT(9, 2, internal)
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SWITCH_PORT(10, 3, internal)
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SWITCH_PORT(11, 4, internal)
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SWITCH_PORT(12, 5, internal)
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SWITCH_PORT(13, 6, internal)
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SWITCH_PORT(14, 7, internal)
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SWITCH_PORT(15, 8, internal)
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SWITCH_SFP_PORT(24, 9, 1000base-x)
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port@26 {
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reg = <26>;
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label = "lan10";
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phy-mode = "1000base-x";
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phy-handle = <&phy26>;
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managed = "in-band-status";
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sfp = <&sfp1>;
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};
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port@28 {
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ethernet = <ðernet0>;
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reg = <28>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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&uart1 {
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status = "okay";
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};
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