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All patches automatically rebased. Build system: x86_64 Build-tested: bcm2711/RPi4B, ramips/tplink_archer-a6-v3, filogic/xiaomi_redmi-router-ax6000-ubootmod Run-tested: bcm2711/RPi4B, ramips/tplink_archer-a6-v3, filogic/xiaomi_redmi-router-ax6000-ubootmod Signed-off-by: John Audia <therealgraysky@proton.me>
74 lines
2.9 KiB
Diff
74 lines
2.9 KiB
Diff
From a1d5ce866f2e2062246343af757c22e9abe4e844 Mon Sep 17 00:00:00 2001
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From: Jonathan Bell <jonathan@raspberrypi.com>
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Date: Mon, 13 Dec 2021 16:04:03 +0000
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Subject: [PATCH] usb: xhci: add VLI_TRB_CACHE_BUG quirk
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The VL805 fetches up to 4 transfer TRBs at a time. TRB reads don't cross
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a 64B boundary, and if a TRB is fetched and is not on a 64B boundary,
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the read is sized up to the next 64B boundary.
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However the VL805 implements a readahead prefetch for TRBs on a transfer
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ring. This fetches the next 64B after any TRB read has happened. Near
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the end of a ring segment, the prefetcher can read the first 64B of the
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next page in physical memory and this is where the behaviour causes a
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bug.
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The controller does not tag reads with which endpoint they are for, so
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if the start of the next page is a ring segment used by a victim
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endpoint, and the victim endpoint is about to fetch TRBs from the start
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of the segment, the victim endpoint will read from the prefetched data
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and not perform a read to main memory. If the data is stale, the ring
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cycle state bit may not be correct and the endpoint will silently halt.
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Adjust trbs_per_seg for transfer rings allocated for this controller.
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See https://github.com/raspberrypi/linux/issues/4685
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Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
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---
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drivers/usb/host/xhci-mem.c | 11 +++++++++++
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drivers/usb/host/xhci-pci.c | 1 +
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drivers/usb/host/xhci.h | 1 +
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3 files changed, 13 insertions(+)
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--- a/drivers/usb/host/xhci-mem.c
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+++ b/drivers/usb/host/xhci-mem.c
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@@ -392,6 +392,17 @@ struct xhci_ring *xhci_ring_alloc(struct
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return ring;
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ring->trbs_per_seg = TRBS_PER_SEGMENT;
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+ /*
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+ * The Via VL805 has a bug where cache readahead will fetch off the end
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+ * of a page if the Link TRB of a transfer ring is in the last 4 slots.
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+ * Where there are consecutive physical pages containing ring segments,
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+ * this can cause a desync between the controller's view of a ring
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+ * and the host.
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+ */
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+ if (xhci->quirks & XHCI_VLI_TRB_CACHE_BUG &&
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+ type != TYPE_EVENT && type != TYPE_COMMAND)
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+ ring->trbs_per_seg -= 4;
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+
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ret = xhci_alloc_segments_for_ring(xhci, &ring->first_seg,
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&ring->last_seg, num_segs, ring->trbs_per_seg,
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cycle_state, type, max_packet, flags);
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--- a/drivers/usb/host/xhci-pci.c
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+++ b/drivers/usb/host/xhci-pci.c
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@@ -298,6 +298,7 @@ static void xhci_pci_quirks(struct devic
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xhci->quirks |= XHCI_LPM_SUPPORT;
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xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS;
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xhci->quirks |= XHCI_AVOID_DQ_ON_LINK;
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+ xhci->quirks |= XHCI_VLI_TRB_CACHE_BUG;
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}
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if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
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--- a/drivers/usb/host/xhci.h
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+++ b/drivers/usb/host/xhci.h
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@@ -1908,6 +1908,7 @@ struct xhci_hcd {
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#define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43)
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#define XHCI_RESET_TO_DEFAULT BIT_ULL(44)
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#define XHCI_AVOID_DQ_ON_LINK BIT_ULL(45)
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+#define XHCI_VLI_TRB_CACHE_BUG BIT_ULL(46)
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unsigned int num_active_eps;
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unsigned int limit_active_eps;
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