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31116661ff
update to the version of the driver that is on its way upstream Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 47898
163 lines
5.1 KiB
Diff
163 lines
5.1 KiB
Diff
From 9c2487f148ee38807d86beaf12dc2b818a764a99 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Tue, 17 Nov 2015 00:20:07 +0100
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Subject: [PATCH 500/513] Documentation: DT: net: add docs for ralink/mediatek
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SoC ethernet binding
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Add three files. ralink,rt2880-net.txt descibes the actual frame engine
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and the other two describe the switch forntend bindings.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
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Signed-off-by: Michael Lee <igvtee@gmail.com>
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Cc: devicetree@vger.kernel.org
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---
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.../bindings/net/mediatek,mt7620-gsw.txt | 26 +++++++++
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.../devicetree/bindings/net/ralink,rt2880-net.txt | 61 ++++++++++++++++++++
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.../devicetree/bindings/net/ralink,rt3050-esw.txt | 32 ++++++++++
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3 files changed, 119 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/net/mediatek,mt7620-gsw.txt
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create mode 100644 Documentation/devicetree/bindings/net/ralink,rt2880-net.txt
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create mode 100644 Documentation/devicetree/bindings/net/ralink,rt3050-esw.txt
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diff --git a/Documentation/devicetree/bindings/net/mediatek,mt7620-gsw.txt b/Documentation/devicetree/bindings/net/mediatek,mt7620-gsw.txt
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new file mode 100644
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index 0000000..fb47d8e
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/net/mediatek,mt7620-gsw.txt
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@@ -0,0 +1,26 @@
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+Mediatek Gigabit Switch
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+=======================
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+
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+The mediatek gigabit switch can be found on Mediatek SoCs (mt7620, mt7621).
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+
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+Required properties:
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+- compatible: Should be "mediatek,mt7620-gsw"
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+- reg: Address and length of the register set for the device
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+- interrupt-parent: Should be the phandle for the interrupt controller
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+ that services interrupts for this device
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+- interrupts: Should contain the gigabit switches interrupt
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+- resets: Should contain the gigabit switches resets
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+- reset-names: Should contain the reset names "gsw"
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+
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+Example:
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+
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+gsw@10110000 {
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+ compatible = "ralink,mt7620-gsw";
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+ reg = <0x10110000 8000>;
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+
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+ resets = <&rstctrl 23>;
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+ reset-names = "gsw";
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <17>;
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+};
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diff --git a/Documentation/devicetree/bindings/net/ralink,rt2880-net.txt b/Documentation/devicetree/bindings/net/ralink,rt2880-net.txt
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new file mode 100644
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index 0000000..88b095d
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/net/ralink,rt2880-net.txt
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@@ -0,0 +1,61 @@
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+Ralink Frame Engine Ethernet controller
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+=======================================
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+
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+The Ralink frame engine ethernet controller can be found on Ralink and
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+Mediatek SoCs (RT288x, RT3x5x, RT366x, RT388x, rt5350, mt7620, mt7621, mt76x8).
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+
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+Depending on the SoC, there is a number of ports connected to the CPU port
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+directly and/or via a (gigabit-)switch.
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+
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+* Ethernet controller node
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+
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+Required properties:
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+- compatible: Should be one of "ralink,rt2880-eth", "ralink,rt3050-eth",
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+ "ralink,rt3050-eth", "ralink,rt3883-eth", "ralink,rt5350-eth",
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+ "mediatek,mt7620-eth", "mediatek,mt7621-eth"
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+- reg: Address and length of the register set for the device
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+- interrupt-parent: Should be the phandle for the interrupt controller
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+ that services interrupts for this device
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+- interrupts: Should contain the frame engines interrupt
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+- resets: Should contain the frame engines resets
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+- reset-names: Should contain the reset names "fe". If a switch is present
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+ "esw" is also required.
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+
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+
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+* Ethernet port node
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+
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+Required properties:
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+- compatible: Should be "ralink,eth-port"
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+- reg: The number of the physical port
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+- phy-handle: reference to the node describing the phy
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+
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+Example:
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+
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+mdio-bus {
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+ ...
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+ phy0: ethernet-phy@0 {
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+ phy-mode = "mii";
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+ reg = <0>;
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+ };
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+};
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+
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+ethernet@400000 {
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+ compatible = "ralink,rt2880-eth";
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+ reg = <0x00400000 10000>;
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+
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ resets = <&rstctrl 18>;
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+ reset-names = "fe";
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+
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+ interrupt-parent = <&cpuintc>;
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+ interrupts = <5>;
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+
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+ port@0 {
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+ compatible = "ralink,eth-port";
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+ reg = <0>;
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+ phy-handle = <&phy0>;
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+ };
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+
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+};
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diff --git a/Documentation/devicetree/bindings/net/ralink,rt3050-esw.txt b/Documentation/devicetree/bindings/net/ralink,rt3050-esw.txt
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new file mode 100644
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index 0000000..ed32e21
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/net/ralink,rt3050-esw.txt
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@@ -0,0 +1,32 @@
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+Ralink Fast Ethernet Embedded Switch
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+====================================
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+
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+The ralink fast ethernet embedded switch can be found on Ralink and Mediatek
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+SoCs (RT3x5x, rt5350, mt76x8).
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+
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+Required properties:
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+- compatible: Should be "ralink,rt3050-esw"
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+- reg: Address and length of the register set for the device
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+- interrupt-parent: Should be the phandle for the interrupt controller
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+ that services interrupts for this device
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+- interrupts: Should contain the embedded switches interrupt
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+- resets: Should contain the embedded switches resets
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+- reset-names: Should contain the reset names "esw"
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+
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+Optional properties:
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+- ralink,portmap: can be used to choose if the default switch setup is
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+ llllw or wllll
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+- ralink,led_polarity: override the active high/low settings of the leds
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+
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+Example:
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+
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+esw@10110000 {
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+ compatible = "ralink,rt3050-esw";
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+ reg = <0x10110000 8000>;
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+
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+ resets = <&rstctrl 23>;
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+ reset-names = "esw";
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <17>;
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+};
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--
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1.7.10.4
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