mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-25 08:21:14 +00:00
f547fc9d57
Use reset controller to reset mt7620 ethernet phy instead of directly writing system control registers. The reset line of "ephy" is 24, so the DTS resets properties have been updated to get the correct reset signal. Tested on HiWiFi HC5861. Signed-off-by: Shiji Yang <yangshiji66@qq.com>
604 lines
9.9 KiB
Plaintext
604 lines
9.9 KiB
Plaintext
/dts-v1/;
|
|
|
|
/ {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "ralink,mt7620a-soc";
|
|
|
|
aliases {
|
|
spi0 = &spi0;
|
|
spi1 = &spi1;
|
|
serial0 = &uartlite;
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
compatible = "mips,mips24KEc";
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
chosen {
|
|
bootargs = "console=ttyS0,57600";
|
|
};
|
|
|
|
cpuintc: cpuintc {
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-controller;
|
|
compatible = "mti,cpu-interrupt-controller";
|
|
};
|
|
|
|
palmbus: palmbus@10000000 {
|
|
compatible = "palmbus";
|
|
reg = <0x10000000 0x200000>;
|
|
ranges = <0x0 0x10000000 0x1FFFFF>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
sysc: syscon@0 {
|
|
compatible = "ralink,mt7620-sysc", "syscon";
|
|
reg = <0x0 0x100>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
timer: timer@100 {
|
|
compatible = "ralink,mt7620a-timer", "ralink,rt2880-timer";
|
|
reg = <0x100 0x20>;
|
|
|
|
clocks = <&sysc 5>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <1>;
|
|
};
|
|
|
|
watchdog: watchdog@120 {
|
|
compatible = "ralink,mt7620a-wdt", "ralink,rt2880-wdt";
|
|
reg = <0x120 0x10>;
|
|
|
|
clocks = <&sysc 6>;
|
|
|
|
resets = <&sysc 8>;
|
|
reset-names = "wdt";
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <1>;
|
|
};
|
|
|
|
intc: intc@200 {
|
|
compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc";
|
|
reg = <0x200 0x100>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
|
|
interrupt-parent = <&cpuintc>;
|
|
interrupts = <2>;
|
|
};
|
|
|
|
memc: memc@300 {
|
|
compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
|
|
reg = <0x300 0x100>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <3>;
|
|
};
|
|
|
|
uart: uart@500 {
|
|
compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
|
|
reg = <0x500 0x100>;
|
|
|
|
clocks = <&sysc 7>;
|
|
|
|
resets = <&sysc 12>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <5>;
|
|
|
|
reg-shift = <2>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio0: gpio@600 {
|
|
compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
|
|
reg = <0x600 0x34>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <6>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
ngpios = <24>;
|
|
ralink,gpio-base = <0>;
|
|
ralink,register-map = [ 00 04 08 0c
|
|
20 24 28 2c
|
|
30 34 ];
|
|
};
|
|
|
|
gpio1: gpio@638 {
|
|
compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
|
|
reg = <0x638 0x24>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <6>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
ngpios = <16>;
|
|
ralink,gpio-base = <24>;
|
|
ralink,register-map = [ 00 04 08 0c
|
|
10 14 18 1c
|
|
20 24 ];
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio2: gpio@660 {
|
|
compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
|
|
reg = <0x660 0x24>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <6>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
ngpios = <32>;
|
|
ralink,gpio-base = <40>;
|
|
ralink,register-map = [ 00 04 08 0c
|
|
10 14 18 1c
|
|
20 24 ];
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio3: gpio@688 {
|
|
compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
|
|
reg = <0x688 0x24>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <6>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
ngpios = <1>;
|
|
ralink,gpio-base = <72>;
|
|
ralink,register-map = [ 00 04 08 0c
|
|
10 14 18 1c
|
|
20 24 ];
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c: i2c@900 {
|
|
compatible = "ralink,rt2880-i2c";
|
|
reg = <0x900 0x100>;
|
|
|
|
clocks = <&sysc 8>;
|
|
|
|
resets = <&sysc 16>;
|
|
reset-names = "i2c";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c_pins>;
|
|
};
|
|
|
|
i2s: i2s@a00 {
|
|
compatible = "mediatek,mt7620-i2s";
|
|
reg = <0xa00 0x100>;
|
|
|
|
clocks = <&sysc 9>;
|
|
|
|
resets = <&sysc 17>;
|
|
reset-names = "i2s";
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <10>;
|
|
|
|
txdma-req = <2>;
|
|
rxdma-req = <3>;
|
|
|
|
dmas = <&gdma 4>,
|
|
<&gdma 6>;
|
|
dma-names = "tx", "rx";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi0: spi@b00 {
|
|
compatible = "ralink,mt7620a-spi", "ralink,rt2880-spi";
|
|
reg = <0xb00 0x40>;
|
|
|
|
clocks = <&sysc 10>;
|
|
|
|
resets = <&sysc 18>;
|
|
reset-names = "spi";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi_pins>;
|
|
};
|
|
|
|
spi1: spi@b40 {
|
|
compatible = "ralink,rt2880-spi";
|
|
reg = <0xb40 0x60>;
|
|
|
|
clocks = <&sysc 11>;
|
|
|
|
resets = <&sysc 18>;
|
|
reset-names = "spi";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi_cs1>;
|
|
};
|
|
|
|
uartlite: uartlite@c00 {
|
|
compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
|
|
reg = <0xc00 0x100>;
|
|
|
|
clocks = <&sysc 12>;
|
|
|
|
resets = <&sysc 19>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <12>;
|
|
|
|
reg-shift = <2>;
|
|
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uartlite_pins>;
|
|
};
|
|
|
|
systick: systick@d00 {
|
|
compatible = "ralink,mt7620a-systick", "ralink,cevt-systick";
|
|
reg = <0xd00 0x10>;
|
|
|
|
interrupt-parent = <&cpuintc>;
|
|
interrupts = <7>;
|
|
};
|
|
|
|
pcm: pcm@2000 {
|
|
compatible = "ralink,mt7620a-pcm";
|
|
reg = <0x2000 0x800>;
|
|
|
|
resets = <&sysc 11>;
|
|
reset-names = "pcm";
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <4>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
gdma: gdma@2800 {
|
|
compatible = "ralink,mt7620a-gdma", "ralink,rt3883-gdma";
|
|
reg = <0x2800 0x800>;
|
|
|
|
resets = <&sysc 14>;
|
|
reset-names = "dma";
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <7>;
|
|
|
|
#dma-cells = <1>;
|
|
#dma-channels = <16>;
|
|
#dma-requests = <16>;
|
|
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
pinctrl: pinctrl {
|
|
compatible = "ralink,rt2880-pinmux";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&state_default>;
|
|
|
|
state_default: pinctrl0 {
|
|
};
|
|
|
|
pcm_i2s_pins: pcm_i2s {
|
|
pcm_i2s {
|
|
groups = "uartf";
|
|
function = "pcm i2s";
|
|
};
|
|
};
|
|
|
|
uartf_gpio_pins: uartf_gpio {
|
|
uartf_gpio {
|
|
groups = "uartf";
|
|
function = "gpio uartf";
|
|
};
|
|
};
|
|
|
|
gpio_i2s_pins: gpio_i2s {
|
|
gpio_i2s {
|
|
groups = "uartf";
|
|
function = "gpio i2s";
|
|
};
|
|
};
|
|
|
|
spi_pins: spi_pins {
|
|
spi_pins {
|
|
groups = "spi";
|
|
function = "spi";
|
|
};
|
|
};
|
|
|
|
spi_cs1: spi1 {
|
|
spi1 {
|
|
groups = "spi refclk";
|
|
function = "spi refclk";
|
|
};
|
|
};
|
|
|
|
i2c_pins: i2c_pins {
|
|
i2c_pins {
|
|
groups = "i2c";
|
|
function = "i2c";
|
|
};
|
|
};
|
|
|
|
uartlite_pins: uartlite {
|
|
uart {
|
|
groups = "uartlite";
|
|
function = "uartlite";
|
|
};
|
|
};
|
|
|
|
mdio_pins: mdio {
|
|
mdio {
|
|
groups = "mdio";
|
|
function = "mdio";
|
|
};
|
|
};
|
|
|
|
mdio_refclk_pins: mdio_refclk {
|
|
mdio_refclk {
|
|
groups = "mdio";
|
|
function = "refclk";
|
|
};
|
|
};
|
|
|
|
ephy_pins: ephy {
|
|
ephy {
|
|
groups = "ephy";
|
|
function = "ephy";
|
|
};
|
|
};
|
|
|
|
wled_pins: wled {
|
|
wled {
|
|
groups = "wled";
|
|
function = "wled";
|
|
};
|
|
};
|
|
|
|
rgmii1_pins: rgmii1 {
|
|
rgmii1 {
|
|
groups = "rgmii1";
|
|
function = "rgmii1";
|
|
};
|
|
};
|
|
|
|
rgmii2_pins: rgmii2 {
|
|
rgmii2 {
|
|
groups = "rgmii2";
|
|
function = "rgmii2";
|
|
};
|
|
};
|
|
|
|
pcie_pins: pcie {
|
|
pcie {
|
|
groups = "pcie";
|
|
function = "pcie rst";
|
|
};
|
|
};
|
|
|
|
pa_pins: pa {
|
|
pa {
|
|
groups = "pa";
|
|
function = "pa";
|
|
};
|
|
};
|
|
|
|
pa_gpio_pins: pa_gpio {
|
|
pa {
|
|
groups = "pa";
|
|
function = "gpio";
|
|
};
|
|
};
|
|
|
|
sdhci_pins: sdhci {
|
|
sdhci {
|
|
groups = "nd_sd";
|
|
function = "sd";
|
|
};
|
|
};
|
|
};
|
|
|
|
usbphy: usbphy {
|
|
compatible = "mediatek,mt7620-usbphy";
|
|
#phy-cells = <0>;
|
|
|
|
ralink,sysctl = <&sysc>;
|
|
/* usb phy reset is only controled by RSTCTRL bit 25 */
|
|
resets = <&sysc 25>, <&sysc 22>;
|
|
reset-names = "host", "device";
|
|
};
|
|
|
|
ethernet: ethernet@10100000 {
|
|
compatible = "mediatek,mt7620-eth";
|
|
reg = <0x10100000 0x10000>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
interrupt-parent = <&cpuintc>;
|
|
interrupts = <5>;
|
|
|
|
resets = <&sysc 21>, <&sysc 23>;
|
|
reset-names = "fe", "esw";
|
|
|
|
mediatek,switch = <&gsw>;
|
|
|
|
port@4 {
|
|
compatible = "mediatek,mt7620a-gsw-port", "mediatek,eth-port";
|
|
reg = <4>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
port@5 {
|
|
compatible = "mediatek,mt7620a-gsw-port", "mediatek,eth-port";
|
|
reg = <5>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
mdio-bus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
gsw: gsw@10110000 {
|
|
compatible = "mediatek,mt7620-gsw";
|
|
reg = <0x10110000 0x8000>;
|
|
|
|
resets = <&sysc 24>;
|
|
reset-names = "ephy";
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <17>;
|
|
};
|
|
|
|
sdhci: sdhci@10130000 {
|
|
compatible = "ralink,mt7620-sdhci";
|
|
reg = <0x10130000 0x4000>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <14>;
|
|
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&sdhci_pins>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
ehci: ehci@101c0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "generic-ehci";
|
|
reg = <0x101c0000 0x1000>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <18>;
|
|
|
|
phys = <&usbphy>;
|
|
phy-names = "usb";
|
|
|
|
status = "disabled";
|
|
|
|
ehci_port1: port@1 {
|
|
reg = <1>;
|
|
#trigger-source-cells = <0>;
|
|
};
|
|
};
|
|
|
|
ohci: ohci@101c1000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "generic-ohci";
|
|
reg = <0x101c1000 0x1000>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <18>;
|
|
|
|
phys = <&usbphy>;
|
|
phy-names = "usb";
|
|
|
|
status = "disabled";
|
|
|
|
ohci_port1: port@1 {
|
|
reg = <1>;
|
|
#trigger-source-cells = <0>;
|
|
};
|
|
};
|
|
|
|
pcie: pcie@10140000 {
|
|
compatible = "mediatek,mt7620-pci";
|
|
reg = <0x10140000 0x100
|
|
0x10142000 0x100>;
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
|
|
resets = <&sysc 26>;
|
|
reset-names = "pcie0";
|
|
|
|
interrupt-parent = <&cpuintc>;
|
|
interrupts = <4>;
|
|
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pcie_pins>;
|
|
|
|
device_type = "pci";
|
|
|
|
bus-range = <0 255>;
|
|
ranges = <
|
|
0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
|
|
0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
|
|
>;
|
|
|
|
status = "disabled";
|
|
|
|
pcie0: pcie@0,0 {
|
|
reg = <0x0000 0 0 0 0>;
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
|
|
device_type = "pci";
|
|
|
|
ranges;
|
|
};
|
|
};
|
|
|
|
wmac: wmac@10180000 {
|
|
compatible = "ralink,rt7620-wmac", "ralink,rt2880-wmac";
|
|
reg = <0x10180000 0x40000>;
|
|
|
|
clocks = <&sysc 13>;
|
|
|
|
interrupt-parent = <&cpuintc>;
|
|
interrupts = <6>;
|
|
|
|
ralink,eeprom = "soc_wmac.eeprom";
|
|
};
|
|
};
|