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28f534d953
Update patch set for new release and add required kernel option CONFIG_ZRAM_TRACK_ENTRY_ACTIME to generic config Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.6.66 Manually rebased: bcm27xx/patches-6.6/950-0092-MMC-added-alternative-MMC-driver.patch bcm53xx/patches-6.6/180-usb-xhci-add-support-for-performing-fake-doorbell.patch starfive/patches-6.6/1000-serial-8250_dw-Add-starfive-jh7100-hsuart-compatible.patch Removed upstreamed: bcm27xx/patches-6.6/950-0029-vc4_hdmi-Avoid-log-spam-for-audio-start-failure.patch[1] All other patches automatically rebased. 1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.66&id=e0388a95736abd1f5f5a94221dd1ac24eacbd4d7 Build system: x86/64 Build-tested: bcm27xx/bcm2712, flogic/glinet_gl-mt6000, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3, x86/64 Run-tested: bcm27xx/bcm2712, flogic/glinet_gl-mt6000, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3, x86/64 Signed-off-by: John Audia <therealgraysky@proton.me> Link: https://github.com/openwrt/openwrt/pull/17271 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
166 lines
6.4 KiB
Diff
166 lines
6.4 KiB
Diff
From efc0d85363a0e089ec3cdd0fbee58b4320fca449 Mon Sep 17 00:00:00 2001
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From: Dom Cobley <popcornmix@gmail.com>
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Date: Fri, 12 Jan 2024 15:48:14 +0000
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Subject: [PATCH 0830/1085] vc4/hvs: Updates to support D0 alpha and csc
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changes
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2712D0 has a simpler colourspace conversion matrix block
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so set that up.
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Signed-off-by: Dom Cobley <popcornmix@gmail.com>
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---
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drivers/gpu/drm/vc4/vc4_hvs.c | 73 ++++++++++++++++++++++-----------
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drivers/gpu/drm/vc4/vc4_plane.c | 20 +++++++--
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drivers/gpu/drm/vc4/vc4_regs.h | 3 ++
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3 files changed, 67 insertions(+), 29 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_hvs.c
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+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
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@@ -1903,6 +1903,17 @@ static int vc4_hvs_hw_init(struct vc4_hv
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#define CFC1_N_MA_CSC_COEFF_C23(x) (0xa03c + ((x) * 0x3000))
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#define CFC1_N_MA_CSC_COEFF_C24(x) (0xa040 + ((x) * 0x3000))
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+#define SCALER_PI_CMP_CSC_RED0(x) (0x200 + ((x) * 0x40))
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+#define SCALER_PI_CMP_CSC_RED1(x) (0x204 + ((x) * 0x40))
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+#define SCALER_PI_CMP_CSC_RED_CLAMP(x) (0x208 + ((x) * 0x40))
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+#define SCALER_PI_CMP_CSC_CFG(x) (0x20c + ((x) * 0x40))
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+#define SCALER_PI_CMP_CSC_GREEN0(x) (0x210 + ((x) * 0x40))
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+#define SCALER_PI_CMP_CSC_GREEN1(x) (0x214 + ((x) * 0x40))
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+#define SCALER_PI_CMP_CSC_GREEN_CLAMP(x) (0x218 + ((x) * 0x40))
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+#define SCALER_PI_CMP_CSC_BLUE0(x) (0x220 + ((x) * 0x40))
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+#define SCALER_PI_CMP_CSC_BLUE1(x) (0x224 + ((x) * 0x40))
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+#define SCALER_PI_CMP_CSC_BLUE_CLAMP(x) (0x228 + ((x) * 0x40))
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+
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/* 4 S2.22 multiplication factors, and 1 S9.15 addititive element for each of 3
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* output components
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*/
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@@ -1973,31 +1984,43 @@ static int vc6_hvs_hw_init(struct vc4_hv
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HVS_WRITE(SCALER6(PRI_MAP0), 0xffffffff);
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HVS_WRITE(SCALER6(PRI_MAP1), 0xffffffff);
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- if (hvs->vc4->step_d0)
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- return;
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-
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- for (i = 0; i < 6; i++) {
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- coeffs = &csc_coeffs[i / 3][i % 3];
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-
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- HVS_WRITE(CFC1_N_MA_CSC_COEFF_C00(i), coeffs->csc[0][0]);
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- HVS_WRITE(CFC1_N_MA_CSC_COEFF_C01(i), coeffs->csc[0][1]);
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- HVS_WRITE(CFC1_N_MA_CSC_COEFF_C02(i), coeffs->csc[0][2]);
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- HVS_WRITE(CFC1_N_MA_CSC_COEFF_C03(i), coeffs->csc[0][3]);
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- HVS_WRITE(CFC1_N_MA_CSC_COEFF_C04(i), coeffs->csc[0][4]);
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-
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- HVS_WRITE(CFC1_N_MA_CSC_COEFF_C10(i), coeffs->csc[1][0]);
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- HVS_WRITE(CFC1_N_MA_CSC_COEFF_C11(i), coeffs->csc[1][1]);
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- HVS_WRITE(CFC1_N_MA_CSC_COEFF_C12(i), coeffs->csc[1][2]);
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- HVS_WRITE(CFC1_N_MA_CSC_COEFF_C13(i), coeffs->csc[1][3]);
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- HVS_WRITE(CFC1_N_MA_CSC_COEFF_C14(i), coeffs->csc[1][4]);
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-
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- HVS_WRITE(CFC1_N_MA_CSC_COEFF_C20(i), coeffs->csc[2][0]);
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- HVS_WRITE(CFC1_N_MA_CSC_COEFF_C21(i), coeffs->csc[2][1]);
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- HVS_WRITE(CFC1_N_MA_CSC_COEFF_C22(i), coeffs->csc[2][2]);
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- HVS_WRITE(CFC1_N_MA_CSC_COEFF_C23(i), coeffs->csc[2][3]);
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- HVS_WRITE(CFC1_N_MA_CSC_COEFF_C24(i), coeffs->csc[2][4]);
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+ if (hvs->vc4->step_d0) {
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+ for (i = 0; i < 8; i++) {
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+ HVS_WRITE(SCALER_PI_CMP_CSC_RED0(i), 0x1f002566);
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+ HVS_WRITE(SCALER_PI_CMP_CSC_RED1(i), 0x3994);
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+ HVS_WRITE(SCALER_PI_CMP_CSC_RED_CLAMP(i), 0xfff00000);
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+ HVS_WRITE(SCALER_PI_CMP_CSC_CFG(i), 0x1);
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+ HVS_WRITE(SCALER_PI_CMP_CSC_GREEN0(i), 0x18002566);
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+ HVS_WRITE(SCALER_PI_CMP_CSC_GREEN1(i), 0xf927eee2);
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+ HVS_WRITE(SCALER_PI_CMP_CSC_GREEN_CLAMP(i), 0xfff00000);
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+ HVS_WRITE(SCALER_PI_CMP_CSC_BLUE0(i), 0x18002566);
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+ HVS_WRITE(SCALER_PI_CMP_CSC_BLUE1(i), 0x43d80000);
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+ HVS_WRITE(SCALER_PI_CMP_CSC_BLUE_CLAMP(i), 0xfff00000);
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+ }
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+ } else {
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+ for (i = 0; i < 6; i++) {
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+ coeffs = &csc_coeffs[i / 3][i % 3];
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+
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+ HVS_WRITE(CFC1_N_MA_CSC_COEFF_C00(i), coeffs->csc[0][0]);
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+ HVS_WRITE(CFC1_N_MA_CSC_COEFF_C01(i), coeffs->csc[0][1]);
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+ HVS_WRITE(CFC1_N_MA_CSC_COEFF_C02(i), coeffs->csc[0][2]);
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+ HVS_WRITE(CFC1_N_MA_CSC_COEFF_C03(i), coeffs->csc[0][3]);
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+ HVS_WRITE(CFC1_N_MA_CSC_COEFF_C04(i), coeffs->csc[0][4]);
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+
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+ HVS_WRITE(CFC1_N_MA_CSC_COEFF_C10(i), coeffs->csc[1][0]);
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+ HVS_WRITE(CFC1_N_MA_CSC_COEFF_C11(i), coeffs->csc[1][1]);
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+ HVS_WRITE(CFC1_N_MA_CSC_COEFF_C12(i), coeffs->csc[1][2]);
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+ HVS_WRITE(CFC1_N_MA_CSC_COEFF_C13(i), coeffs->csc[1][3]);
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+ HVS_WRITE(CFC1_N_MA_CSC_COEFF_C14(i), coeffs->csc[1][4]);
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+
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+ HVS_WRITE(CFC1_N_MA_CSC_COEFF_C20(i), coeffs->csc[2][0]);
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+ HVS_WRITE(CFC1_N_MA_CSC_COEFF_C21(i), coeffs->csc[2][1]);
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+ HVS_WRITE(CFC1_N_MA_CSC_COEFF_C22(i), coeffs->csc[2][2]);
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+ HVS_WRITE(CFC1_N_MA_CSC_COEFF_C23(i), coeffs->csc[2][3]);
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+ HVS_WRITE(CFC1_N_MA_CSC_COEFF_C24(i), coeffs->csc[2][4]);
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- HVS_WRITE(CFC1_N_NL_CSC_CTRL(i), BIT(15));
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+ HVS_WRITE(CFC1_N_NL_CSC_CTRL(i), BIT(15));
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+ }
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}
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return 0;
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--- a/drivers/gpu/drm/vc4/vc4_plane.c
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+++ b/drivers/gpu/drm/vc4/vc4_plane.c
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@@ -1080,6 +1080,12 @@ static u32 vc4_hvs5_get_alpha_blend_mode
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WARN_ON_ONCE(vc4->gen != VC4_GEN_5 && vc4->gen != VC4_GEN_6);
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+ if (vc4->gen == VC4_GEN_6 && vc4->step_d0) {
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+ return state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI ?
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+ SCALER5_CTL2_ALPHA_PREMULT : 0;
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+ }
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+
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+
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if (!state->fb->format->has_alpha)
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return VC4_SET_FIELD(SCALER5_CTL2_ALPHA_MODE_FIXED,
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SCALER5_CTL2_ALPHA_MODE);
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@@ -1595,14 +1601,13 @@ static int vc4_plane_mode_set(struct drm
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static u32 vc6_plane_get_csc_mode(struct vc4_plane_state *vc4_state)
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{
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struct drm_plane_state *state = &vc4_state->base;
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+ struct vc4_dev *vc4 = to_vc4_dev(state->plane->dev);
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u32 ret = 0;
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if (vc4_state->is_yuv) {
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enum drm_color_encoding color_encoding = state->color_encoding;
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enum drm_color_range color_range = state->color_range;
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- ret |= SCALER6_CTL2_CSC_ENABLE;
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-
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/* CSC pre-loaded with:
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* 0 = BT601 limited range
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* 1 = BT709 limited range
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@@ -1616,8 +1621,15 @@ static u32 vc6_plane_get_csc_mode(struct
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if (color_range > DRM_COLOR_YCBCR_FULL_RANGE)
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color_range = DRM_COLOR_YCBCR_LIMITED_RANGE;
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- ret |= VC4_SET_FIELD(color_encoding + (color_range * 3),
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- SCALER6_CTL2_BRCM_CFC_CONTROL);
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+ if (vc4->step_d0) {
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+ ret |= SCALER6D0_CTL2_CSC_ENABLE;
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+ ret |= VC4_SET_FIELD(color_encoding + (color_range * 3),
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+ SCALER6D0_CTL2_BRCM_CFC_CONTROL);
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+ } else {
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+ ret |= SCALER6_CTL2_CSC_ENABLE;
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+ ret |= VC4_SET_FIELD(color_encoding + (color_range * 3),
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+ SCALER6_CTL2_BRCM_CFC_CONTROL);
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+ }
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}
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return ret;
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--- a/drivers/gpu/drm/vc4/vc4_regs.h
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+++ b/drivers/gpu/drm/vc4/vc4_regs.h
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@@ -1417,6 +1417,9 @@ enum hvs_pixel_format {
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#define SCALER6_CTL2_BRCM_CFC_CONTROL_MASK VC4_MASK(18, 16)
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#define SCALER6_CTL2_ALPHA_MASK VC4_MASK(15, 4)
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+#define SCALER6D0_CTL2_CSC_ENABLE BIT(19)
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+#define SCALER6D0_CTL2_BRCM_CFC_CONTROL_MASK VC4_MASK(22, 20)
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+
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#define SCALER6_POS1_SCL_LINES_MASK VC4_MASK(28, 16)
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#define SCALER6_POS1_SCL_WIDTH_MASK VC4_MASK(12, 0)
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