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451b51f0dc
Manual adapted the following patches:
generic/hack-5.15/221-module_exports.patch
bcm27xx/patches-5.15/950-0008-drm-vc4-hdmi-Use-a-mutex-to-prevent-concurrent-frame.patch
octeontx/patches-5.15/0004-PCI-add-quirk-for-Gateworks-PLX-PEX860x-switch-with-.patch
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
(cherry picked from commit 9693ed6a9e)
42 lines
2.1 KiB
Diff
42 lines
2.1 KiB
Diff
From da76cb63d04dc22ed32123b8c1d084c006d67bfb Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Mon, 7 Nov 2022 14:29:01 +0100
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Subject: [PATCH] clk: qcom: ipq8074: add missing networking resets
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Downstream QCA 5.4 kernel defines networking resets which are not present
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in the mainline kernel but are required for the networking drivers.
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So, port the downstream resets and avoid using magic values for mask,
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construct mask for resets which require multiple bits to be set/cleared.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Link: https://lore.kernel.org/r/20221107132901.489240-3-robimarko@gmail.com
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---
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drivers/clk/qcom/gcc-ipq8074.c | 14 ++++++++++++++
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1 file changed, 14 insertions(+)
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--- a/drivers/clk/qcom/gcc-ipq8074.c
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+++ b/drivers/clk/qcom/gcc-ipq8074.c
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@@ -4667,6 +4667,20 @@ static const struct qcom_reset_map gcc_i
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[GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
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[GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
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[GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
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+ [GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = GENMASK(19, 16) },
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+ [GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = GENMASK(13, 4) | BIT(1) },
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+ [GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
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+ [GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = GENMASK(5, 4) | BIT(1) },
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+ [GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
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+ [GCC_UNIPHY2_SOFT_RESET] = { .reg = 0x56204, .bitmask = GENMASK(5, 4) | BIT(1) },
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+ [GCC_UNIPHY2_XPCS_RESET] = { 0x56204, 2 },
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+ [GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = GENMASK(21, 20) },
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+ [GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = BIT(24) | GENMASK(1, 0) },
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+ [GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = BIT(25) | GENMASK(3, 2) },
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+ [GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = BIT(26) | GENMASK(5, 4) },
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+ [GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = BIT(27) | GENMASK(9, 8) },
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+ [GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = BIT(28) | GENMASK(11, 10) },
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+ [GCC_NSSPORT6_RESET] = { .reg = 0x68014, .bitmask = BIT(29) | GENMASK(13, 12) },
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};
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static struct gdsc *gcc_ipq8074_gdscs[] = {
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