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e3a1e78cd8
It compiles but *doesn't* boot so it isn't enabled yet. Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
185 lines
3.7 KiB
Diff
185 lines
3.7 KiB
Diff
From 527a3ac9bdf81da4b7160ce3cea57f28a0e5eb64 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
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Date: Wed, 13 Jan 2021 12:14:06 +0100
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Subject: [PATCH] arm64: dts: broadcom: bcm4908: describe internal switch
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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BCM4908 has internal switch with 5 GPHYs. Ports 0 - 3 are always
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connected to the internal PHYs. Remaining ports depend on device setup.
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Asus GT-AC5300 has an extra switch with its PHYs accessible using the
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internal MDIO.
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CPU port and Ethernet interface remain to be documented.
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Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
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Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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---
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.../bcm4908/bcm4908-asus-gt-ac5300.dts | 51 +++++++++++
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.../boot/dts/broadcom/bcm4908/bcm4908.dtsi | 85 ++++++++++++++++++-
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2 files changed, 135 insertions(+), 1 deletion(-)
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--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts
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+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts
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@@ -44,6 +44,57 @@
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};
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};
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+&ports {
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+ port@0 {
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+ label = "lan2";
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+ };
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+
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+ port@1 {
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+ label = "lan1";
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+ };
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+
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+ port@2 {
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+ label = "lan6";
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+ };
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+
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+ port@3 {
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+ label = "lan5";
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+ };
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+
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+ /* External BCM53134S switch */
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+ port@7 {
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+ label = "sw";
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+ reg = <7>;
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+
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+ fixed-link {
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+ speed = <1000>;
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+ full-duplex;
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+ };
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+ };
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+};
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+
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+&mdio {
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+ /* lan8 */
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+ ethernet-phy@0 {
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+ reg = <0>;
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+ };
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+
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+ /* lan7 */
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+ ethernet-phy@1 {
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+ reg = <1>;
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+ };
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+
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+ /* lan4 */
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+ ethernet-phy@2 {
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+ reg = <2>;
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+ };
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+
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+ /* lan3 */
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+ ethernet-phy@3 {
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+ reg = <3>;
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+ };
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+};
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+
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&nandcs {
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
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+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
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@@ -108,7 +108,7 @@
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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- ranges = <0x00 0x00 0x80000000 0x10000>;
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+ ranges = <0x00 0x00 0x80000000 0xd0000>;
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usb@c300 {
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compatible = "generic-ehci";
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@@ -130,6 +130,89 @@
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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+
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+ ethernet-switch@80000 {
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+ compatible = "simple-bus";
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+ #size-cells = <1>;
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+ #address-cells = <1>;
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+ ranges = <0 0x80000 0x50000>;
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+
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+ ethernet-switch@0 {
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+ compatible = "brcm,bcm4908-switch";
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+ reg = <0x0 0x40000>,
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+ <0x40000 0x110>,
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+ <0x40340 0x30>,
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+ <0x40380 0x30>,
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+ <0x40600 0x34>,
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+ <0x40800 0x208>;
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+ reg-names = "core", "reg", "intrl2_0",
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+ "intrl2_1", "fcb", "acb";
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+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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+ brcm,num-gphy = <5>;
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+ brcm,num-rgmii-ports = <2>;
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+
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ ports: ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ port@0 {
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+ reg = <0>;
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+ phy-mode = "internal";
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+ phy-handle = <&phy8>;
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+ };
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+
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+ port@1 {
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+ reg = <1>;
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+ phy-mode = "internal";
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+ phy-handle = <&phy9>;
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+ };
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+
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+ port@2 {
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+ reg = <2>;
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+ phy-mode = "internal";
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+ phy-handle = <&phy10>;
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+ };
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+
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+ port@3 {
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+ reg = <3>;
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+ phy-mode = "internal";
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+ phy-handle = <&phy11>;
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+ };
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+ };
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+ };
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+
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+ mdio: mdio@405c0 {
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+ compatible = "brcm,unimac-mdio";
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+ reg = <0x405c0 0x8>;
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+ reg-names = "mdio";
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+ #size-cells = <0>;
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+ #address-cells = <1>;
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+
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+ phy8: ethernet-phy@8 {
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+ reg = <8>;
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+ };
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+
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+ phy9: ethernet-phy@9 {
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+ reg = <9>;
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+ };
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+
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+ phy10: ethernet-phy@a {
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+ reg = <10>;
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+ };
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+
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+ phy11: ethernet-phy@b {
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+ reg = <11>;
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+ };
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+
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+ phy12: ethernet-phy@c {
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+ reg = <12>;
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+ };
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+ };
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+ };
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};
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bus@ff800000 {
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