mirror of
https://github.com/openwrt/openwrt.git
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2c35899d81
All modification made by update_kernel.sh in a fresh clone without
existing toolchains.
Build system: x86_64
Build-tested: ipq806x/R7800, bcm27xx/bcm2711
Run-tested: ipq806x/R7800
Compile-tested [*]: ath79/{tiny,generic}, ipq40xx, octeon,
ramips/mt7621, realtek, x86/64
Run-tested [*]: ath79/generic, ipq40xx, octeon, ramips/mt7621
No dmesg regressions, everything functional
Signed-off-by: John Audia <graysky@archlinux.us>
Tested-by: Stijn Segers <foss@volatilesystems.org> [*]
88 lines
3.4 KiB
Diff
88 lines
3.4 KiB
Diff
From e870793b277eeaf3c455971d9610f039fd9ab160 Mon Sep 17 00:00:00 2001
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From: Vladimir Oltean <vladimir.oltean@nxp.com>
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Date: Thu, 14 Nov 2019 17:03:23 +0200
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Subject: [PATCH] net: mscc: ocelot: create a helper for changing the port MTU
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Since in an NPI/DSA setup, not all ports will have the same MTU, we need
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to make sure the watermarks for pause frames and/or tail dropping logic
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that existed in the driver is still coherent for the new MTU values.
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We need to do this because the NPI (aka external CPU) port needs an
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increased MTU for the DSA tag. This will be done in a future patch.
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Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/ethernet/mscc/ocelot.c | 40 ++++++++++++++++++++++----------------
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1 file changed, 23 insertions(+), 17 deletions(-)
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--- a/drivers/net/ethernet/mscc/ocelot.c
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+++ b/drivers/net/ethernet/mscc/ocelot.c
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@@ -2099,11 +2099,32 @@ static int ocelot_init_timestamp(struct
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return 0;
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}
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-static void ocelot_init_port(struct ocelot *ocelot, int port)
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+static void ocelot_port_set_mtu(struct ocelot *ocelot, int port, size_t mtu)
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{
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struct ocelot_port *ocelot_port = ocelot->ports[port];
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int atop_wm;
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+ ocelot_port_writel(ocelot_port, mtu, DEV_MAC_MAXLEN_CFG);
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+
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+ /* Set Pause WM hysteresis
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+ * 152 = 6 * mtu / OCELOT_BUFFER_CELL_SZ
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+ * 101 = 4 * mtu / OCELOT_BUFFER_CELL_SZ
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+ */
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+ ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA |
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+ SYS_PAUSE_CFG_PAUSE_STOP(101) |
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+ SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, port);
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+
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+ /* Tail dropping watermark */
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+ atop_wm = (ocelot->shared_queue_sz - 9 * mtu) / OCELOT_BUFFER_CELL_SZ;
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+ ocelot_write_rix(ocelot, ocelot_wm_enc(9 * mtu),
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+ SYS_ATOP, port);
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+ ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG);
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+}
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+
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+static void ocelot_init_port(struct ocelot *ocelot, int port)
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+{
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+ struct ocelot_port *ocelot_port = ocelot->ports[port];
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+
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INIT_LIST_HEAD(&ocelot_port->skbs);
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/* Basic L2 initialization */
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@@ -2124,8 +2145,7 @@ static void ocelot_init_port(struct ocel
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DEV_MAC_HDX_CFG);
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/* Set Max Length and maximum tags allowed */
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- ocelot_port_writel(ocelot_port, VLAN_ETH_FRAME_LEN,
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- DEV_MAC_MAXLEN_CFG);
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+ ocelot_port_set_mtu(ocelot, port, VLAN_ETH_FRAME_LEN);
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ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
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DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
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DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
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@@ -2135,20 +2155,6 @@ static void ocelot_init_port(struct ocel
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ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
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ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG);
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- /* Set Pause WM hysteresis
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- * 152 = 6 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
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- * 101 = 4 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
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- */
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- ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA |
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- SYS_PAUSE_CFG_PAUSE_STOP(101) |
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- SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, port);
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-
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- /* Tail dropping watermark */
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- atop_wm = (ocelot->shared_queue_sz - 9 * VLAN_ETH_FRAME_LEN) / OCELOT_BUFFER_CELL_SZ;
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- ocelot_write_rix(ocelot, ocelot_wm_enc(9 * VLAN_ETH_FRAME_LEN),
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- SYS_ATOP, port);
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- ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG);
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-
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/* Drop frames with multicast source address */
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ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
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ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
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