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290a6527be
Each individual device DTS now enables either pcie0 or pcie1. Signed-off-by: Michael Pratt <mcpratt@pm.me>
137 lines
2.2 KiB
Plaintext
137 lines
2.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "qca955x_senao_loader.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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compatible = "watchguard,ap300", "qca,qca9558";
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model = "WatchGuard AP300";
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aliases {
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label-mac-device = ð0;
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led-boot = &led_power;
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led-failsafe = &led_power;
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led-running = &led_power;
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led-upgrade = &led_power;
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};
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keys {
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compatible = "gpio-keys";
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reset {
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linux,code = <KEY_RESTART>;
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gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
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debounce-interval = <60>;
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};
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};
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leds {
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compatible = "gpio-leds";
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led_power: power {
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label = "green:power";
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gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
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default-state = "on";
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};
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lan_data {
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label = "orange:lan_data";
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gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
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};
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lan_link {
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label = "green:lan_link";
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gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
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};
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wifi_amber {
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label = "amber:wifi";
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gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "phy1tpt";
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};
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wifi_green {
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label = "green:wifi";
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gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "phy0tpt";
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};
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};
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virtual_flash {
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devices = <&fwconcat0 &fwconcat1 &fwconcat2>;
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};
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watchdog {
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compatible = "linux,wdt-gpio";
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gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
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hw_algo = "toggle";
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hw_margin_ms = <20000>;
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always-running;
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};
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};
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ð0 {
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status = "okay";
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nvmem-cells = <&macaddr_art_0>;
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nvmem-cell-names = "mac-address";
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phy-handle = <&phy5>;
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phy-mode = "rgmii-id";
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pll-data = <0x82000000 0x80000101 0x80001313>;
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};
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&mdio0 {
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status = "okay";
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phy5: ethernet-phy@5 {
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reg = <5>;
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eee-broken-100tx;
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eee-broken-1000t;
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};
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};
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&partitions {
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fwconcat2: partition@ff0000 {
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label = "fwconcat2";
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reg = <0xff0000 0x1000000>;
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};
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art: partition@1ff0000 {
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label = "art";
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reg = <0x1ff0000 0x010000>;
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read-only;
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};
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};
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&wdt {
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status = "disabled";
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};
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&wmac {
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status = "okay";
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mtd-cal-data = <&art 0x1000>;
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nvmem-cells = <&macaddr_art_0>;
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nvmem-cell-names = "mac-address";
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mac-address-increment = <1>;
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};
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&pcie0 {
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status = "okay";
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};
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&art {
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compatible = "nvmem-cells";
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#address-cells = <1>;
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#size-cells = <1>;
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macaddr_art_0: macaddr@0 {
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reg = <0x0 0x6>;
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};
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};
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