mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-23 15:32:33 +00:00
54b275c8ed
Signed-off-by: Christian Lamparter <chunkeey@gmail.com> Signed-off-by: Mathias Kresin <dev@kresin.me> Signed-off-by: John Crispin <john@phrozen.org>
131 lines
3.3 KiB
Diff
131 lines
3.3 KiB
Diff
From ea5f4d6f4716f3a0bb4fc3614b7a0e8c0df1cb81 Mon Sep 17 00:00:00 2001
|
|
From: Matthew McClintock <mmcclint@codeaurora.org>
|
|
Date: Thu, 17 Mar 2016 16:22:28 -0500
|
|
Subject: [PATCH] qcom: ipq4019: add USB nodes to ipq4019 SoC device tree
|
|
|
|
This adds the SoC nodes to the ipq4019 device tree and
|
|
enable it for the DK01.1 board.
|
|
|
|
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
|
|
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
|
---
|
|
Changes:
|
|
- replaced space with tab
|
|
- added sleep and mock_utmi clocks
|
|
- added registers for usb2 and usb3 parent node
|
|
- changed compatible to qca,ipa4019-dwc3
|
|
- updated usb2 and usb3 names
|
|
(included the reg - in case they become necessary later)
|
|
---
|
|
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 20 ++++++++
|
|
arch/arm/boot/dts/qcom-ipq4019.dtsi | 71 +++++++++++++++++++++++++++
|
|
2 files changed, 91 insertions(+)
|
|
|
|
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
|
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
|
|
@@ -101,5 +101,25 @@
|
|
wifi@a800000 {
|
|
status = "ok";
|
|
};
|
|
+
|
|
+ usb3_ss_phy: ssphy@9a000 {
|
|
+ status = "ok";
|
|
+ };
|
|
+
|
|
+ usb3_hs_phy: hsphy@a6000 {
|
|
+ status = "ok";
|
|
+ };
|
|
+
|
|
+ usb3: usb3@8af8800 {
|
|
+ status = "ok";
|
|
+ };
|
|
+
|
|
+ usb2_hs_phy: hsphy@a8000 {
|
|
+ status = "ok";
|
|
+ };
|
|
+
|
|
+ usb2: usb2@60f8800 {
|
|
+ status = "ok";
|
|
+ };
|
|
};
|
|
};
|
|
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
|
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
|
@@ -538,5 +538,76 @@
|
|
"legacy";
|
|
status = "disabled";
|
|
};
|
|
+
|
|
+ usb3_ss_phy: ssphy@9a000 {
|
|
+ compatible = "qca,uni-ssphy";
|
|
+ reg = <0x9a000 0x800>;
|
|
+ reg-names = "phy_base";
|
|
+ resets = <&gcc USB3_UNIPHY_PHY_ARES>;
|
|
+ reset-names = "por_rst";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usb3_hs_phy: hsphy@a6000 {
|
|
+ compatible = "qca,baldur-usb3-hsphy";
|
|
+ reg = <0xa6000 0x40>;
|
|
+ reg-names = "phy_base";
|
|
+ resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
|
|
+ reset-names = "por_rst", "srif_rst";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usb3@8af8800 {
|
|
+ compatible = "qca,ipq4019-dwc3";
|
|
+ reg = <0x8af8800 0x100>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ clocks = <&gcc GCC_USB3_MASTER_CLK>,
|
|
+ <&gcc GCC_USB3_SLEEP_CLK>,
|
|
+ <&gcc GCC_USB3_MOCK_UTMI_CLK>;
|
|
+ clock-names = "master", "sleep", "mock_utmi";
|
|
+ ranges;
|
|
+ status = "disabled";
|
|
+
|
|
+ dwc3@8a00000 {
|
|
+ compatible = "snps,dwc3";
|
|
+ reg = <0x8a00000 0xf8000>;
|
|
+ interrupts = <0 132 0>;
|
|
+ usb-phy = <&usb3_hs_phy>, <&usb3_ss_phy>;
|
|
+ phy-names = "usb2-phy", "usb3-phy";
|
|
+ dr_mode = "host";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usb2_hs_phy: hsphy@a8000 {
|
|
+ compatible = "qca,baldur-usb2-hsphy";
|
|
+ reg = <0xa8000 0x40>;
|
|
+ reg-names = "phy_base";
|
|
+ resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
|
|
+ reset-names = "por_rst", "srif_rst";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usb2@60f8800 {
|
|
+ compatible = "qca,ipq4019-dwc3";
|
|
+ reg = <0x60f8800 0x100>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ clocks = <&gcc GCC_USB2_MASTER_CLK>,
|
|
+ <&gcc GCC_USB2_SLEEP_CLK>,
|
|
+ <&gcc GCC_USB2_MOCK_UTMI_CLK>;
|
|
+ clock-names = "master", "sleep", "mock_utmi";
|
|
+ ranges;
|
|
+ status = "disabled";
|
|
+
|
|
+ dwc3@6000000 {
|
|
+ compatible = "snps,dwc3";
|
|
+ reg = <0x6000000 0xf8000>;
|
|
+ interrupts = <0 136 0>;
|
|
+ usb-phy = <&usb2_hs_phy>;
|
|
+ phy-names = "usb2-phy";
|
|
+ dr_mode = "host";
|
|
+ };
|
|
+ };
|
|
};
|
|
};
|