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There's an interaction issue between the clk changes:" clk: qcom: ipq4019: Add the apss cpu pll divider clock node clk: qcom: ipq4019: remove fixed clocks and add pll clocks " and the cpufreq-dt. cpufreq-dt is now spamming the kernel-log with the following: [ 1099.190658] cpu cpu0: dev_pm_opp_set_rate: failed to find current OPP for freq 761142857 (-34) This only happens on certain devices like the Compex WPJ428 and AVM FritzBox!4040. However, other devices like the Asus RT-AC58U and Meraki MR33 work just fine. The issue stem from the fact that all higher CPU-Clocks are achieved by switching the clock-parent to the P_DDRPLLAPSS (ddrpllapss). Which is set by Qualcomm's proprietary bootcode as part of the DDR calibration. For example, the FB4040 uses 256 MiB Nanya NT5CC128M16IP clocked at round 533 MHz (ddrpllsdcc = 190285714 Hz). whereas the 128 MiB Nanya NT5CC64M16GP-DI in the ASUS RT-AC58U is clocked at a slightly higher 537 MHz ( ddrpllsdcc = 192000000 Hz). Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
78 lines
1.8 KiB
Diff
78 lines
1.8 KiB
Diff
From 18c3b42575a154343831aec0637aab00e19440e1 Mon Sep 17 00:00:00 2001
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From: Matthew McClintock <mmcclint@codeaurora.org>
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Date: Thu, 17 Mar 2016 15:01:09 -0500
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Subject: [PATCH 17/69] qcom: ipq4019: add cpu operating points for cpufreq
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support
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This adds some operating points for cpu frequeny scaling
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Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
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---
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arch/arm/boot/dts/qcom-ipq4019.dtsi | 34 ++++++++++++++++++++++++++--------
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1 file changed, 26 insertions(+), 8 deletions(-)
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--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
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@@ -40,14 +40,7 @@
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reg = <0x0>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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- operating-points = <
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- /* kHz uV (fixed) */
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- 48000 1100000
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- 200000 1100000
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- 500000 1100000
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- 666000 1100000
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- >;
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- clock-latency = <256000>;
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+ operating-points-v2 = <&cpu0_opp_table>;
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};
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cpu@1 {
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@@ -59,6 +52,7 @@
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reg = <0x1>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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+ operating-points-v2 = <&cpu0_opp_table>;
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};
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cpu@2 {
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@@ -70,6 +64,7 @@
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reg = <0x2>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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+ operating-points-v2 = <&cpu0_opp_table>;
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};
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cpu@3 {
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@@ -81,6 +76,29 @@
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reg = <0x3>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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+ operating-points-v2 = <&cpu0_opp_table>;
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+ };
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+ };
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+
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+ cpu0_opp_table: opp_table0 {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ opp-48000000 {
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+ opp-hz = /bits/ 64 <48000000>;
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+ clock-latency-ns = <256000>;
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+ };
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+ opp-200000000 {
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+ opp-hz = /bits/ 64 <200000000>;
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+ clock-latency-ns = <256000>;
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+ };
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+ opp-500000000 {
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+ opp-hz = /bits/ 64 <500000000>;
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+ clock-latency-ns = <256000>;
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+ };
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+ opp-716000000 {
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+ opp-hz = /bits/ 64 <716000000>;
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+ clock-latency-ns = <256000>;
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};
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};
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