mirror of
https://github.com/openwrt/openwrt.git
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9b1b89229f
Removed upstreamed patches:
pending-5.4/499-mtd-parser-cmdline-Fix-parsing-of-part-names-with-co.patch
Manually merged:
pending-5.4/611-netfilter_match_bypass_default_table.patch
layerscape/302-dts-0112-arm64-dts-fsl-ls1028a-prepare-dts-for-overlay.patch
Build-tested: ipq806x/R7800, bcm27xx/bcm2711, ath79/{generic,tiny},
ipq40xx, octeon, ramips/mt7621, realtek, x86/64
Run-tested: ipq806x/R7800, realtek
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Tested-by: John Audia <graysky@archlinux.us>
Tested-by: Stijn Segers <foss@volatilesystems.org>
103 lines
2.8 KiB
Diff
103 lines
2.8 KiB
Diff
From f5f011742b6ec9ad1db54de9e8296f1d5a3ede8a Mon Sep 17 00:00:00 2001
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From: Claudiu Manoil <claudiu.manoil@nxp.com>
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Date: Fri, 14 Jun 2019 19:24:27 +0300
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Subject: [PATCH] arm64: dts: fsl: ls1028a: Add Felix switch port DT node
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Add the switch device node, available on PF5, so that the
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switch port sub-nodes (net devices) can be linked to
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corresponding board specific phy nodes (external ports) or
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have their link mode defined (internal ports).
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The switch device features 6 ports, 4 with external links
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and 2 internally facing to the ls1028a SoC and connected via
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fixed links to 2 internal enetc ethernet contoller ports.
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Add the corresponding enetc internal port device nodes,
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mapped to PF2 and PF6 PCIe functions.
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And don't forget to enable the 4MB BAR4 in the root complex
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ECAM space, where the switch registers are mapped.
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Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
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---
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arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 58 +++++++++++++++++++++++++-
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1 file changed, 57 insertions(+), 1 deletion(-)
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
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@@ -750,7 +750,9 @@
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/* PF1: VF0-1 BAR0 - non-prefetchable memory */
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0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000
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/* PF1: VF0-1 BAR2 - prefetchable memory */
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- 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000>;
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+ 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000
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+ /* BAR4 (PF5) - non-prefetchable memory */
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+ 0x82000000 0x0 0x00000000 0x1 0xfc000000 0x0 0x400000>;
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enetc_port0: ethernet@0,0 {
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compatible = "fsl,enetc";
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@@ -766,12 +768,66 @@
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#address-cells = <1>;
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#size-cells = <0>;
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};
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+ ethernet@0,2 {
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+ compatible = "fsl,enetc";
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+ reg = <0x000200 0 0 0 0>;
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+ fixed-link {
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+ speed = <1000>;
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+ full-duplex;
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+ };
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+ };
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ethernet@0,4 {
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compatible = "fsl,enetc-ptp";
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reg = <0x000400 0 0 0 0>;
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clocks = <&clockgen 2 3>;
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little-endian;
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};
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+ switch@0,5 {
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+ compatible = "mscc,felix-switch";
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+ reg = <0x000500 0 0 0 0>;
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ /* external ports */
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+ switch_port0: port@0 {
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+ reg = <0>;
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+ };
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+ switch_port1: port@1 {
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+ reg = <1>;
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+ };
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+ switch_port2: port@2 {
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+ reg = <2>;
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+ };
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+ switch_port3: port@3 {
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+ reg = <3>;
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+ };
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+ /* internal to-cpu ports */
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+ port@4 {
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+ reg = <4>;
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+ fixed-link {
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+ speed = <1000>;
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+ full-duplex;
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+ };
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+ };
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+ port@5 {
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+ reg = <5>;
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+ fixed-link {
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+ speed = <1000>;
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+ full-duplex;
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+ };
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+ };
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+ };
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+ };
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+ ethernet@0,6 {
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+ compatible = "fsl,enetc";
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+ reg = <0x000600 0 0 0 0>;
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+ fixed-link {
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+ speed = <1000>;
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+ full-duplex;
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+ };
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+ };
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};
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rcpm: rcpm@1e34040 {
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