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8f8d5decc9
Removed because they are upstream:
generic/backport-5.15/704-15-v5.19-net-mtk_eth_soc-move-MAC_MCR-setting-to-mac_finish.patch
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=linux-5.15.y&id=c5c0760adc260d55265c086b9efb350ea6dda38b
generic/pending-5.15/735-net-mediatek-mtk_eth_soc-release-MAC_MCR_FORCE_LINK-.patch
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=linux-5.15.y&id=448cc8b5f743985f6d1d98aa4efb386fef4c3bf2
generic/pending-5.15/736-net-ethernet-mtk_eth_soc-fix-PPE-hanging-issue.patch
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=linux-5.15.y&id=9fcadd125044007351905d40c405fadc2d3bb6d6
Add new configuration symbols for tegra target.
Tested-by: Stijn Segers <foss@volatilesystems.org>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
(cherry picked from commit fb2c6e9d4d)
333 lines
9.3 KiB
Diff
333 lines
9.3 KiB
Diff
From: Chuanjia Liu <chuanjia.liu@mediatek.com>
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Date: Mon, 23 Aug 2021 11:27:59 +0800
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Subject: [PATCH] arm64: dts: mediatek: Split PCIe node for MT2712 and MT7622
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There are two independent PCIe controllers in MT2712 and MT7622
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platform. Each of them should contain an independent MSI domain.
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In old dts architecture, MSI domain will be inherited from the root
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bridge, and all of the devices will share the same MSI domain.
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Hence that, the PCIe devices will not work properly if the irq number
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which required is more than 32.
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Split the PCIe node for MT2712 and MT7622 platform to comply with
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the hardware design and fix MSI issue.
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Signed-off-by: Chuanjia Liu <chuanjia.liu@mediatek.com>
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Acked-by: Ryder Lee <ryder.lee@mediatek.com>
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Link: https://lore.kernel.org/r/20210823032800.1660-6-chuanjia.liu@mediatek.com
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Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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---
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--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
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@@ -915,64 +915,67 @@
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};
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};
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- pcie: pcie@11700000 {
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+ pcie1: pcie@112ff000 {
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compatible = "mediatek,mt2712-pcie";
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device_type = "pci";
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- reg = <0 0x11700000 0 0x1000>,
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- <0 0x112ff000 0 0x1000>;
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- reg-names = "port0", "port1";
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+ reg = <0 0x112ff000 0 0x1000>;
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+ reg-names = "port1";
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+ linux,pci-domain = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
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- <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
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- <&pericfg CLK_PERI_PCIE0>,
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+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "pcie_irq";
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+ clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
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<&pericfg CLK_PERI_PCIE1>;
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- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
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- phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>;
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- phy-names = "pcie-phy0", "pcie-phy1";
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+ clock-names = "sys_ck1", "ahb_ck1";
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+ phys = <&u3port1 PHY_TYPE_PCIE>;
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+ phy-names = "pcie-phy1";
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bus-range = <0x00 0xff>;
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- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
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+ ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>;
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+ status = "disabled";
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- pcie0: pcie@0,0 {
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- device_type = "pci";
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- status = "disabled";
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- reg = <0x0000 0 0 0 0>;
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- #address-cells = <3>;
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- #size-cells = <2>;
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 7>;
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+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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+ <0 0 0 2 &pcie_intc1 1>,
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+ <0 0 0 3 &pcie_intc1 2>,
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+ <0 0 0 4 &pcie_intc1 3>;
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+ pcie_intc1: interrupt-controller {
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+ interrupt-controller;
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+ #address-cells = <0>;
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#interrupt-cells = <1>;
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- ranges;
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- interrupt-map-mask = <0 0 0 7>;
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- interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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- <0 0 0 2 &pcie_intc0 1>,
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- <0 0 0 3 &pcie_intc0 2>,
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- <0 0 0 4 &pcie_intc0 3>;
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- pcie_intc0: interrupt-controller {
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- interrupt-controller;
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- #address-cells = <0>;
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- #interrupt-cells = <1>;
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- };
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};
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+ };
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+
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+ pcie0: pcie@11700000 {
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+ compatible = "mediatek,mt2712-pcie";
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+ device_type = "pci";
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+ reg = <0 0x11700000 0 0x1000>;
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+ reg-names = "port0";
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+ linux,pci-domain = <0>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "pcie_irq";
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+ clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
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+ <&pericfg CLK_PERI_PCIE0>;
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+ clock-names = "sys_ck0", "ahb_ck0";
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+ phys = <&u3port0 PHY_TYPE_PCIE>;
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+ phy-names = "pcie-phy0";
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+ bus-range = <0x00 0xff>;
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+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
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+ status = "disabled";
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- pcie1: pcie@1,0 {
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- device_type = "pci";
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- status = "disabled";
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- reg = <0x0800 0 0 0 0>;
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- #address-cells = <3>;
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- #size-cells = <2>;
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 7>;
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+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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+ <0 0 0 2 &pcie_intc0 1>,
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+ <0 0 0 3 &pcie_intc0 2>,
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+ <0 0 0 4 &pcie_intc0 3>;
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+ pcie_intc0: interrupt-controller {
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+ interrupt-controller;
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+ #address-cells = <0>;
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#interrupt-cells = <1>;
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- ranges;
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- interrupt-map-mask = <0 0 0 7>;
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- interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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- <0 0 0 2 &pcie_intc1 1>,
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- <0 0 0 3 &pcie_intc1 2>,
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- <0 0 0 4 &pcie_intc1 3>;
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- pcie_intc1: interrupt-controller {
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- interrupt-controller;
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- #address-cells = <0>;
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- #interrupt-cells = <1>;
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- };
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};
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};
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--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
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+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
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@@ -303,18 +303,16 @@
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};
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};
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-&pcie {
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+&pcie0 {
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pinctrl-names = "default";
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- pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
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+ pinctrl-0 = <&pcie0_pins>;
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status = "okay";
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+};
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- pcie@0,0 {
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- status = "okay";
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- };
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-
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- pcie@1,0 {
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- status = "okay";
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- };
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+&pcie1 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pcie1_pins>;
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+ status = "okay";
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};
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&pio {
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--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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@@ -233,18 +233,16 @@
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};
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};
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-&pcie {
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+&pcie0 {
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pinctrl-names = "default";
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- pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
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+ pinctrl-0 = <&pcie0_pins>;
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status = "okay";
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+};
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- pcie@0,0 {
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- status = "okay";
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- };
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-
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- pcie@1,0 {
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- status = "okay";
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- };
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+&pcie1 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pcie1_pins>;
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+ status = "okay";
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};
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&pio {
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--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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@@ -809,75 +809,83 @@
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#reset-cells = <1>;
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};
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- pcie: pcie@1a140000 {
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+ pciecfg: pciecfg@1a140000 {
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+ compatible = "mediatek,generic-pciecfg", "syscon";
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+ reg = <0 0x1a140000 0 0x1000>;
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+ };
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+
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+ pcie0: pcie@1a143000 {
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compatible = "mediatek,mt7622-pcie";
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device_type = "pci";
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- reg = <0 0x1a140000 0 0x1000>,
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- <0 0x1a143000 0 0x1000>,
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- <0 0x1a145000 0 0x1000>;
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- reg-names = "subsys", "port0", "port1";
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+ reg = <0 0x1a143000 0 0x1000>;
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+ reg-names = "port0";
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+ linux,pci-domain = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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- interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
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- <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
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+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
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+ interrupt-names = "pcie_irq";
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clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
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- <&pciesys CLK_PCIE_P1_MAC_EN>,
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- <&pciesys CLK_PCIE_P0_AHB_EN>,
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<&pciesys CLK_PCIE_P0_AHB_EN>,
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<&pciesys CLK_PCIE_P0_AUX_EN>,
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- <&pciesys CLK_PCIE_P1_AUX_EN>,
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<&pciesys CLK_PCIE_P0_AXI_EN>,
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- <&pciesys CLK_PCIE_P1_AXI_EN>,
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<&pciesys CLK_PCIE_P0_OBFF_EN>,
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- <&pciesys CLK_PCIE_P1_OBFF_EN>,
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- <&pciesys CLK_PCIE_P0_PIPE_EN>,
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- <&pciesys CLK_PCIE_P1_PIPE_EN>;
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- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
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- "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
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- "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
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+ <&pciesys CLK_PCIE_P0_PIPE_EN>;
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+ clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
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+ "axi_ck0", "obff_ck0", "pipe_ck0";
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+
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power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
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bus-range = <0x00 0xff>;
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- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
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+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
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status = "disabled";
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- pcie0: pcie@0,0 {
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- reg = <0x0000 0 0 0 0>;
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- #address-cells = <3>;
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- #size-cells = <2>;
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 7>;
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+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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+ <0 0 0 2 &pcie_intc0 1>,
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+ <0 0 0 3 &pcie_intc0 2>,
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+ <0 0 0 4 &pcie_intc0 3>;
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+ pcie_intc0: interrupt-controller {
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+ interrupt-controller;
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+ #address-cells = <0>;
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#interrupt-cells = <1>;
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- ranges;
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- status = "disabled";
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-
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- interrupt-map-mask = <0 0 0 7>;
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- interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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- <0 0 0 2 &pcie_intc0 1>,
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- <0 0 0 3 &pcie_intc0 2>,
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- <0 0 0 4 &pcie_intc0 3>;
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- pcie_intc0: interrupt-controller {
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- interrupt-controller;
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- #address-cells = <0>;
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- #interrupt-cells = <1>;
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- };
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};
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+ };
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- pcie1: pcie@1,0 {
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- reg = <0x0800 0 0 0 0>;
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- #address-cells = <3>;
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- #size-cells = <2>;
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- #interrupt-cells = <1>;
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- ranges;
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- status = "disabled";
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+ pcie1: pcie@1a145000 {
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+ compatible = "mediatek,mt7622-pcie";
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+ device_type = "pci";
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+ reg = <0 0x1a145000 0 0x1000>;
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+ reg-names = "port1";
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+ linux,pci-domain = <1>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
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+ interrupt-names = "pcie_irq";
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+ clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
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+ /* designer has connect RC1 with p0_ahb clock */
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+ <&pciesys CLK_PCIE_P0_AHB_EN>,
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+ <&pciesys CLK_PCIE_P1_AUX_EN>,
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+ <&pciesys CLK_PCIE_P1_AXI_EN>,
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+ <&pciesys CLK_PCIE_P1_OBFF_EN>,
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+ <&pciesys CLK_PCIE_P1_PIPE_EN>;
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+ clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
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+ "axi_ck1", "obff_ck1", "pipe_ck1";
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+
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+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
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+ bus-range = <0x00 0xff>;
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+ ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
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+ status = "disabled";
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- interrupt-map-mask = <0 0 0 7>;
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- interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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- <0 0 0 2 &pcie_intc1 1>,
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- <0 0 0 3 &pcie_intc1 2>,
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- <0 0 0 4 &pcie_intc1 3>;
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- pcie_intc1: interrupt-controller {
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- interrupt-controller;
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- #address-cells = <0>;
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- #interrupt-cells = <1>;
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- };
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 7>;
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+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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+ <0 0 0 2 &pcie_intc1 1>,
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+ <0 0 0 3 &pcie_intc1 2>,
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+ <0 0 0 4 &pcie_intc1 3>;
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+ pcie_intc1: interrupt-controller {
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+ interrupt-controller;
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+ #address-cells = <0>;
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+ #interrupt-cells = <1>;
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};
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};
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