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46 lines
1.9 KiB
Diff
46 lines
1.9 KiB
Diff
From 91a49481af7332853c4c921d46aded8210572210 Mon Sep 17 00:00:00 2001
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From: Claudiu Beznea <claudiu.beznea@microchip.com>
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Date: Mon, 11 Oct 2021 14:27:17 +0300
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Subject: [PATCH 245/247] clk: at91: sama7g5: remove prescaler part of master
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clock
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On SAMA7G5 the prescaler part of master clock has been implemented as a
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changeable one. Everytime the prescaler is changed the PMC_SR.MCKRDY bit
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must be polled. Value 1 for PMC_SR.MCKRDY means the prescaler update is
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done. Driver polls for this bit until it becomes 1. On SAMA7G5 it has
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been discovered that in some conditions the PMC_SR.MCKRDY is not rising
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but the rate it provides it's stable. The workaround is to add a timeout
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when polling for PMC_SR.MCKRDY. At the moment, for SAMA7G5, the prescaler
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will be removed from Linux clock tree as all the frequencies for CPU could
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be obtained from PLL and also there will be less overhead when changing
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frequency via DVFS.
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Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
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Link: https://lore.kernel.org/r/20211011112719.3951784-14-claudiu.beznea@microchip.com
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Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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drivers/clk/at91/sama7g5.c | 11 +----------
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1 file changed, 1 insertion(+), 10 deletions(-)
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--- a/drivers/clk/at91/sama7g5.c
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+++ b/drivers/clk/at91/sama7g5.c
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@@ -992,16 +992,7 @@ static void __init sama7g5_pmc_setup(str
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}
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parent_names[0] = "cpupll_divpmcck";
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- hw = at91_clk_register_master_pres(regmap, "cpuck", 1, parent_names,
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- &mck0_layout, &mck0_characteristics,
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- &pmc_mck0_lock,
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- CLK_SET_RATE_PARENT, 0);
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- if (IS_ERR(hw))
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- goto err_free;
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-
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- sama7g5_pmc->chws[PMC_CPU] = hw;
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-
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- hw = at91_clk_register_master_div(regmap, "mck0", "cpuck",
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+ hw = at91_clk_register_master_div(regmap, "mck0", "cpupll_divpmcck",
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&mck0_layout, &mck0_characteristics,
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&pmc_mck0_lock, CLK_GET_RATE_NOCACHE, 5);
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if (IS_ERR(hw))
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