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https://github.com/openwrt/openwrt.git
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9a038e7fd1
Copy config and patches from kernel 5.10 to kernel 5.15 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
296 lines
8.6 KiB
Diff
296 lines
8.6 KiB
Diff
From 5654ec78dd7e64b1e04777b24007344329e6a63b Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Thu, 14 Oct 2021 00:39:11 +0200
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Subject: net: dsa: qca8k: rework rgmii delay logic and scan for cpu port 6
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Future proof commit. This switch have 2 CPU ports and one valid
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configuration is first CPU port set to sgmii and second CPU port set to
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rgmii-id. The current implementation detects delay only for CPU port
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zero set to rgmii and doesn't count any delay set in a secondary CPU
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port. Drop the current delay scan function and move it to the sgmii
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parser function to generalize and implicitly add support for secondary
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CPU port set to rgmii-id. Introduce new logic where delay is enabled
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also with internal delay binding declared and rgmii set as PHY mode.
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/dsa/qca8k.c | 165 ++++++++++++++++++++++++------------------------
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drivers/net/dsa/qca8k.h | 10 ++-
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2 files changed, 89 insertions(+), 86 deletions(-)
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--- a/drivers/net/dsa/qca8k.c
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+++ b/drivers/net/dsa/qca8k.c
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@@ -889,68 +889,6 @@ qca8k_setup_mdio_bus(struct qca8k_priv *
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}
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static int
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-qca8k_setup_of_rgmii_delay(struct qca8k_priv *priv)
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-{
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- struct device_node *port_dn;
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- phy_interface_t mode;
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- struct dsa_port *dp;
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- u32 val;
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-
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- /* CPU port is already checked */
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- dp = dsa_to_port(priv->ds, 0);
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-
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- port_dn = dp->dn;
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-
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- /* Check if port 0 is set to the correct type */
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- of_get_phy_mode(port_dn, &mode);
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- if (mode != PHY_INTERFACE_MODE_RGMII_ID &&
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- mode != PHY_INTERFACE_MODE_RGMII_RXID &&
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- mode != PHY_INTERFACE_MODE_RGMII_TXID) {
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- return 0;
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- }
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-
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- switch (mode) {
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- case PHY_INTERFACE_MODE_RGMII_ID:
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- case PHY_INTERFACE_MODE_RGMII_RXID:
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- if (of_property_read_u32(port_dn, "rx-internal-delay-ps", &val))
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- val = 2;
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- else
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- /* Switch regs accept value in ns, convert ps to ns */
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- val = val / 1000;
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-
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- if (val > QCA8K_MAX_DELAY) {
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- dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value");
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- val = 3;
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- }
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-
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- priv->rgmii_rx_delay = val;
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- /* Stop here if we need to check only for rx delay */
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- if (mode != PHY_INTERFACE_MODE_RGMII_ID)
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- break;
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-
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- fallthrough;
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- case PHY_INTERFACE_MODE_RGMII_TXID:
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- if (of_property_read_u32(port_dn, "tx-internal-delay-ps", &val))
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- val = 1;
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- else
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- /* Switch regs accept value in ns, convert ps to ns */
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- val = val / 1000;
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-
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- if (val > QCA8K_MAX_DELAY) {
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- dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value");
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- val = 3;
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- }
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-
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- priv->rgmii_tx_delay = val;
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- break;
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- default:
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- return 0;
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- }
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-
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- return 0;
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-}
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-
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-static int
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qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv)
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{
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u32 mask = 0;
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@@ -996,19 +934,21 @@ static int qca8k_find_cpu_port(struct ds
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static int
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qca8k_parse_port_config(struct qca8k_priv *priv)
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{
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+ int port, cpu_port_index = 0, ret;
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struct device_node *port_dn;
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phy_interface_t mode;
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struct dsa_port *dp;
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- int port, ret;
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+ u32 delay;
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/* We have 2 CPU port. Check them */
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- for (port = 0; port < QCA8K_NUM_PORTS; port++) {
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+ for (port = 0; port < QCA8K_NUM_PORTS && cpu_port_index < QCA8K_NUM_CPU_PORTS; port++) {
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/* Skip every other port */
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if (port != 0 && port != 6)
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continue;
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dp = dsa_to_port(priv->ds, port);
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port_dn = dp->dn;
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+ cpu_port_index++;
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if (!of_device_is_available(port_dn))
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continue;
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@@ -1017,12 +957,54 @@ qca8k_parse_port_config(struct qca8k_pri
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if (ret)
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continue;
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- if (mode == PHY_INTERFACE_MODE_SGMII) {
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+ switch (mode) {
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+ case PHY_INTERFACE_MODE_RGMII:
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+ case PHY_INTERFACE_MODE_RGMII_ID:
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+ case PHY_INTERFACE_MODE_RGMII_TXID:
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+ case PHY_INTERFACE_MODE_RGMII_RXID:
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+ delay = 0;
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+
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+ if (!of_property_read_u32(port_dn, "tx-internal-delay-ps", &delay))
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+ /* Switch regs accept value in ns, convert ps to ns */
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+ delay = delay / 1000;
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+ else if (mode == PHY_INTERFACE_MODE_RGMII_ID ||
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+ mode == PHY_INTERFACE_MODE_RGMII_TXID)
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+ delay = 1;
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+
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+ if (delay > QCA8K_MAX_DELAY) {
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+ dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value");
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+ delay = 3;
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+ }
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+
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+ priv->rgmii_tx_delay[cpu_port_index] = delay;
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+
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+ delay = 0;
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+
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+ if (!of_property_read_u32(port_dn, "rx-internal-delay-ps", &delay))
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+ /* Switch regs accept value in ns, convert ps to ns */
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+ delay = delay / 1000;
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+ else if (mode == PHY_INTERFACE_MODE_RGMII_ID ||
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+ mode == PHY_INTERFACE_MODE_RGMII_RXID)
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+ delay = 2;
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+
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+ if (delay > QCA8K_MAX_DELAY) {
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+ dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value");
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+ delay = 3;
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+ }
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+
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+ priv->rgmii_rx_delay[cpu_port_index] = delay;
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+
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+ break;
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+ case PHY_INTERFACE_MODE_SGMII:
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if (of_property_read_bool(port_dn, "qca,sgmii-txclk-falling-edge"))
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priv->sgmii_tx_clk_falling_edge = true;
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if (of_property_read_bool(port_dn, "qca,sgmii-rxclk-falling-edge"))
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priv->sgmii_rx_clk_falling_edge = true;
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+
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+ break;
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+ default:
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+ continue;
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}
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}
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@@ -1059,10 +1041,6 @@ qca8k_setup(struct dsa_switch *ds)
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if (ret)
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return ret;
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- ret = qca8k_setup_of_rgmii_delay(priv);
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- if (ret)
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- return ret;
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-
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ret = qca8k_setup_mac_pwr_sel(priv);
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if (ret)
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return ret;
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@@ -1229,8 +1207,8 @@ qca8k_phylink_mac_config(struct dsa_swit
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const struct phylink_link_state *state)
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{
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struct qca8k_priv *priv = ds->priv;
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- u32 reg, val;
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- int ret;
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+ int cpu_port_index, ret;
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+ u32 reg, val, delay;
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switch (port) {
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case 0: /* 1st CPU port */
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@@ -1242,6 +1220,7 @@ qca8k_phylink_mac_config(struct dsa_swit
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return;
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reg = QCA8K_REG_PORT0_PAD_CTRL;
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+ cpu_port_index = QCA8K_CPU_PORT0;
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break;
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case 1:
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case 2:
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@@ -1260,6 +1239,7 @@ qca8k_phylink_mac_config(struct dsa_swit
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return;
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reg = QCA8K_REG_PORT6_PAD_CTRL;
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+ cpu_port_index = QCA8K_CPU_PORT6;
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break;
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default:
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dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
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@@ -1274,23 +1254,40 @@ qca8k_phylink_mac_config(struct dsa_swit
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switch (state->interface) {
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case PHY_INTERFACE_MODE_RGMII:
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- /* RGMII mode means no delay so don't enable the delay */
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- qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN);
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- break;
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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- /* RGMII_ID needs internal delay. This is enabled through
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- * PORT5_PAD_CTRL for all ports, rather than individual port
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- * registers
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+ val = QCA8K_PORT_PAD_RGMII_EN;
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+
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+ /* Delay can be declared in 3 different way.
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+ * Mode to rgmii and internal-delay standard binding defined
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+ * rgmii-id or rgmii-tx/rx phy mode set.
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+ * The parse logic set a delay different than 0 only when one
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+ * of the 3 different way is used. In all other case delay is
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+ * not enabled. With ID or TX/RXID delay is enabled and set
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+ * to the default and recommended value.
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+ */
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+ if (priv->rgmii_tx_delay[cpu_port_index]) {
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+ delay = priv->rgmii_tx_delay[cpu_port_index];
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+
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+ val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) |
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+ QCA8K_PORT_PAD_RGMII_TX_DELAY_EN;
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+ }
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+
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+ if (priv->rgmii_rx_delay[cpu_port_index]) {
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+ delay = priv->rgmii_rx_delay[cpu_port_index];
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+
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+ val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) |
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+ QCA8K_PORT_PAD_RGMII_RX_DELAY_EN;
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+ }
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+
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+ /* Set RGMII delay based on the selected values */
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+ qca8k_write(priv, reg, val);
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+
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+ /* QCA8337 requires to set rgmii rx delay for all ports.
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+ * This is enabled through PORT5_PAD_CTRL for all ports,
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+ * rather than individual port registers.
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*/
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- qca8k_write(priv, reg,
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- QCA8K_PORT_PAD_RGMII_EN |
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- QCA8K_PORT_PAD_RGMII_TX_DELAY(priv->rgmii_tx_delay) |
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- QCA8K_PORT_PAD_RGMII_RX_DELAY(priv->rgmii_rx_delay) |
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- QCA8K_PORT_PAD_RGMII_TX_DELAY_EN |
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- QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
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- /* QCA8337 requires to set rgmii rx delay */
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if (priv->switch_id == QCA8K_ID_QCA8337)
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qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
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QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
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--- a/drivers/net/dsa/qca8k.h
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+++ b/drivers/net/dsa/qca8k.h
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@@ -13,6 +13,7 @@
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#include <linux/gpio.h>
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#define QCA8K_NUM_PORTS 7
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+#define QCA8K_NUM_CPU_PORTS 2
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#define QCA8K_MAX_MTU 9000
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#define PHY_ID_QCA8327 0x004dd034
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@@ -255,13 +256,18 @@ struct qca8k_match_data {
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u8 id;
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};
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+enum {
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+ QCA8K_CPU_PORT0,
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+ QCA8K_CPU_PORT6,
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+};
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+
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struct qca8k_priv {
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u8 switch_id;
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u8 switch_revision;
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- u8 rgmii_tx_delay;
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- u8 rgmii_rx_delay;
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bool sgmii_rx_clk_falling_edge;
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bool sgmii_tx_clk_falling_edge;
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+ u8 rgmii_rx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */
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+ u8 rgmii_tx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */
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bool legacy_phy_port_mapping;
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struct regmap *regmap;
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struct mii_bus *bus;
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