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4295485719
Boot tested on Raspberry Pi B+ (BCM2708) and Raspberry Pi 2 (BCM2709) Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
100 lines
2.8 KiB
Diff
100 lines
2.8 KiB
Diff
From 9c8894afe627b270aad44c64f4e70c659468d7ed Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>
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Date: Fri, 23 Oct 2015 16:26:55 +0200
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Subject: [PATCH 009/703] irqchip: irq-bcm2835: Add 2836 FIQ support
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
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---
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drivers/irqchip/irq-bcm2835.c | 43 +++++++++++++++++++++++++++++++++--
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1 file changed, 41 insertions(+), 2 deletions(-)
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--- a/drivers/irqchip/irq-bcm2835.c
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+++ b/drivers/irqchip/irq-bcm2835.c
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@@ -50,8 +50,11 @@
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#include <linux/of_irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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+#include <linux/mfd/syscon.h>
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+#include <linux/regmap.h>
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#include <asm/exception.h>
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+#include <asm/mach/irq.h>
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/* Put the bank and irq (32 bits) into the hwirq */
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#define MAKE_HWIRQ(b, n) (((b) << 5) | (n))
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@@ -69,6 +72,9 @@
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#define BANK0_VALID_MASK (BANK0_HWIRQ_MASK | BANK1_HWIRQ | BANK2_HWIRQ \
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| SHORTCUT1_MASK | SHORTCUT2_MASK)
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+#undef ARM_LOCAL_GPU_INT_ROUTING
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+#define ARM_LOCAL_GPU_INT_ROUTING 0x0c
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+
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#define REG_FIQ_CONTROL 0x0c
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#define REG_FIQ_ENABLE 0x80
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#define REG_FIQ_DISABLE 0
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@@ -94,6 +100,7 @@ struct armctrl_ic {
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void __iomem *enable[NR_BANKS];
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void __iomem *disable[NR_BANKS];
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struct irq_domain *domain;
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+ struct regmap *local_regmap;
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};
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static struct armctrl_ic intc __read_mostly;
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@@ -127,12 +134,35 @@ static void armctrl_mask_irq(struct irq_
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static void armctrl_unmask_irq(struct irq_data *d)
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{
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- if (d->hwirq >= NUMBER_IRQS)
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+ if (d->hwirq >= NUMBER_IRQS) {
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+ if (num_online_cpus() > 1) {
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+ unsigned int data;
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+ int ret;
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+
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+ if (!intc.local_regmap) {
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+ pr_err("FIQ is disabled due to missing regmap\n");
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+ return;
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+ }
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+
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+ ret = regmap_read(intc.local_regmap,
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+ ARM_LOCAL_GPU_INT_ROUTING, &data);
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+ if (ret) {
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+ pr_err("Failed to read int routing %d\n", ret);
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+ return;
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+ }
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+
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+ data &= ~0xc;
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+ data |= (1 << 2);
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+ regmap_write(intc.local_regmap,
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+ ARM_LOCAL_GPU_INT_ROUTING, data);
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+ }
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+
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writel_relaxed(REG_FIQ_ENABLE | hwirq_to_fiq(d->hwirq),
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intc.base + REG_FIQ_CONTROL);
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- else
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+ } else {
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writel_relaxed(HWIRQ_BIT(d->hwirq),
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intc.enable[HWIRQ_BANK(d->hwirq)]);
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+ }
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}
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static struct irq_chip armctrl_chip = {
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@@ -209,6 +239,15 @@ static int __init armctrl_of_init(struct
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set_handle_irq(bcm2835_handle_irq);
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}
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+ if (is_2836) {
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+ intc.local_regmap =
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+ syscon_regmap_lookup_by_compatible("brcm,bcm2836-arm-local");
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+ if (IS_ERR(intc.local_regmap)) {
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+ pr_err("Failed to get local register map. FIQ is disabled for cpus > 1\n");
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+ intc.local_regmap = NULL;
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+ }
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+ }
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+
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/* Make a duplicate irq range which is used to enable FIQ */
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for (b = 0; b < NR_BANKS; b++) {
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for (i = 0; i < bank_irqs[b]; i++) {
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