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4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
1035 lines
27 KiB
Diff
1035 lines
27 KiB
Diff
From 16e358dcf5e072c82f643d11add5b7e55b36a6f8 Mon Sep 17 00:00:00 2001
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From: "shanlong.li" <shanlong.li@starfivetech.com>
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Date: Wed, 31 May 2023 01:53:31 -0700
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Subject: [PATCH 098/122] riscv: dts: starfive: Add full support for JH7110 and
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VisionFive 2 board
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Merge all StarFive dts patches together.
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Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
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---
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.../jh7110-starfive-visionfive-2-v1.3b.dts | 8 +-
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.../jh7110-starfive-visionfive-2.dtsi | 338 ++++++++++++
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arch/riscv/boot/dts/starfive/jh7110.dtsi | 506 +++++++++++++++++-
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3 files changed, 847 insertions(+), 5 deletions(-)
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--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts
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+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts
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@@ -28,8 +28,8 @@
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motorcomm,tx-clk-adj-enabled;
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motorcomm,tx-clk-100-inverted;
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motorcomm,tx-clk-1000-inverted;
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- rx-clk-driver-strength = <0x6>;
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- rx-data-driver-strength = <0x3>;
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+ motorcomm,rx-clk-driver-strength = <0x6>;
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+ motorcomm,rx-data-driver-strength = <0x3>;
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rx-internal-delay-ps = <1500>;
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tx-internal-delay-ps = <1500>;
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};
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@@ -37,8 +37,8 @@
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&phy1 {
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motorcomm,tx-clk-adj-enabled;
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motorcomm,tx-clk-100-inverted;
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- rx-clk-driver-strength = <0x6>;
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- rx-data-driver-strength = <0x3>;
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+ motorcomm,rx-clk-driver-strength = <0x6>;
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+ motorcomm,rx-data-driver-strength = <0x3>;
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rx-internal-delay-ps = <300>;
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tx-internal-delay-ps = <0>;
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};
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--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
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+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
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@@ -33,11 +33,64 @@
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reg = <0x0 0x40000000 0x1 0x0>;
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};
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+ reserved-memory {
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+
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+ linux,cma {
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+ compatible = "shared-dma-pool";
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+ reusable;
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+ size = <0x0 0x20000000>;
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+ alignment = <0x0 0x1000>;
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+ alloc-ranges = <0x0 0x80000000 0x0 0x20000000>;
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+ linux,cma-default;
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+ };
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+ };
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+
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+ thermal-zones {
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+ cpu-thermal {
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+ polling-delay-passive = <250>;
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+ polling-delay = <15000>;
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+
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+ thermal-sensors = <&sfctemp>;
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+
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+ cooling-maps {
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+ };
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+
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+ trips {
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+ cpu_alert0: cpu_alert0 {
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+ /* milliCelsius */
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+ temperature = <75000>;
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+ hysteresis = <2000>;
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+ type = "passive";
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+ };
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+
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+ cpu_crit: cpu_crit {
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+ /* milliCelsius */
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+ temperature = <90000>;
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+ hysteresis = <2000>;
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+ type = "critical";
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+ };
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+ };
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+ };
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+ };
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+
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gpio-restart {
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compatible = "gpio-restart";
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gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
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priority = <224>;
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};
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+
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+ clk_ext_camera: clk_ext_camera {
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+ compatible = "fixed-clock";
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+ #clock-cells = <0>;
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+ clock-frequency = <24000000>;
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+ };
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+};
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+
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+&dvp_clk {
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+ clock-frequency = <74250000>;
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};
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&gmac0_rgmii_rxin {
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@@ -56,6 +109,10 @@
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clock-frequency = <50000000>;
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};
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+&hdmitx0_pixelclk {
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+ clock-frequency = <297000000>;
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+};
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+
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&i2srx_bclk_ext {
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clock-frequency = <12288000>;
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};
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@@ -88,6 +145,39 @@
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clock-frequency = <49152000>;
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};
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+&csi2rx {
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+ status = "okay";
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+
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+ assigned-clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>;
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+ assigned-clock-rates = <297000000>;
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ port@0 {
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+ reg = <0>;
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+
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+ csi2rx_from_imx219: endpoint {
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+ remote-endpoint = <&imx219_to_csi2rx>;
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+ bus-type = <4>;
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+ clock-lanes = <0>;
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+ data-lanes = <1 2>;
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+ status = "okay";
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+ };
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+ };
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+
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+ port@1 {
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+ reg = <1>;
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+
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+ csi2rx_to_vin: endpoint {
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+ remote-endpoint = <&vin_from_csi2rx>;
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+ status = "okay";
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+ };
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+ };
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+ };
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+};
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+
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&gmac0 {
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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@@ -148,6 +238,20 @@
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pinctrl-names = "default";
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pinctrl-0 = <&i2c5_pins>;
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status = "okay";
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+
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+ axp15060: pmic@36 {
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+ compatible = "x-powers,axp15060";
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+ reg = <0x36>;
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+
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+ regulators {
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+ vdd_cpu: dcdc2 {
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+ regulator-always-on;
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+ regulator-min-microvolt = <500000>;
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+ regulator-max-microvolt = <1540000>;
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+ regulator-name = "vdd-cpu";
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+ };
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+ };
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+ };
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};
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&i2c6 {
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@@ -158,6 +262,121 @@
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pinctrl-names = "default";
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pinctrl-0 = <&i2c6_pins>;
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status = "okay";
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+
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+ imx219: imx219@10 {
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+ compatible = "sony,imx219";
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+ reg = <0x10>;
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+ clocks = <&clk_ext_camera>;
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+ reset-gpio = <&sysgpio 18 0>;
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+ rotation = <0>;
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+ orientation = <1>;
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+
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+ port {
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+ imx219_to_csi2rx: endpoint {
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+ remote-endpoint = <&csi2rx_from_imx219>;
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+ bus-type = <4>;
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+ clock-lanes = <0>;
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+ data-lanes = <1 2>;
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+ link-frequencies = /bits/ 64 <456000000>;
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+ };
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+ };
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+ };
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+};
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+
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+&mmc0 {
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+ max-frequency = <100000000>;
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+ bus-width = <8>;
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+ cap-mmc-highspeed;
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+ mmc-ddr-1_8v;
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+ mmc-hs200-1_8v;
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+ non-removable;
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+ cap-mmc-hw-reset;
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+ post-power-on-delay-ms = <200>;
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+ status = "okay";
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+};
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+
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+&mmc1 {
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+ max-frequency = <100000000>;
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+ bus-width = <4>;
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+ no-sdio;
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+ no-mmc;
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+ broken-cd;
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+ cap-sd-highspeed;
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+ post-power-on-delay-ms = <200>;
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+ status = "okay";
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+};
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+
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+&pcie0 {
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+ pinctrl-names = "default";
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+ reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
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+ phys = <&pciephy0>;
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+ status = "okay";
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+};
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+
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+&pcie1 {
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+ pinctrl-names = "default";
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+ reset-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
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+ phys = <&pciephy1>;
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+ status = "okay";
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+};
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+
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+&ptc {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pwm_pins>;
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+ status = "okay";
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+};
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+
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+&qspi {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ nor_flash: flash@0 {
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+ compatible = "jedec,spi-nor";
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+ reg=<0>;
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+ cdns,read-delay = <5>;
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+ spi-max-frequency = <12000000>;
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+ cdns,tshsl-ns = <1>;
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+ cdns,tsd2d-ns = <1>;
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+ cdns,tchsh-ns = <1>;
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+ cdns,tslch-ns = <1>;
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+
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+ partitions {
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+ compatible = "fixed-partitions";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ spl@0 {
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+ reg = <0x0 0x20000>;
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+ };
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+ uboot@100000 {
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+ reg = <0x100000 0x300000>;
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+ };
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+ data@f00000 {
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+ reg = <0xf00000 0x100000>;
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+ };
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+ };
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+ };
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+};
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+
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+&stfcamss {
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+ status = "okay";
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ port@1 {
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+ reg = <1>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ vin_from_csi2rx: endpoint@1 {
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+ reg = <1>;
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+ remote-endpoint = <&csi2rx_to_vin>;
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+ status = "okay";
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+ };
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+ };
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+ };
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};
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&sysgpio {
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@@ -217,6 +436,98 @@
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};
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};
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+ pcie0_wake_default: pcie0_wake_default {
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+ wake-pins {
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+ pinmux = <GPIOMUX(32, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
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+ bias-disable;
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+ drive-strength = <2>;
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+ input-enable;
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+ input-schmitt-disable;
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+ slew-rate = <0>;
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+ };
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+ };
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+
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+ pcie0_clkreq_default: pcie0_clkreq_default {
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+ clkreq-pins {
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+ bias-disable;
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+ pinmux = <GPIOMUX(27, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
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+ drive-strength = <2>;
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+ input-enable;
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+ input-schmitt-disable;
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+ slew-rate = <0>;
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+ };
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+ };
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+
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+ pcie1_wake_default: pcie1_wake_default {
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+ wake-pins {
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+ bias-disable;
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+ pinmux = <GPIOMUX(21, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
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+ drive-strength = <2>;
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+ input-enable;
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+ input-schmitt-disable;
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+ slew-rate = <0>;
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+ };
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+ };
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+
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+ pcie1_clkreq_default: pcie1_clkreq_default {
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+ clkreq-pins {
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+ bias-disable;
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+ pinmux = <GPIOMUX(29, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
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+ drive-strength = <2>;
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+ input-enable;
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+ input-schmitt-disable;
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+ slew-rate = <0>;
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+ };
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+ };
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+
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+ pwm_pins: pwm-0 {
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+ pwm-pins {
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+ pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0,
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+ GPOEN_SYS_PWM0_CHANNEL0, GPI_NONE)>,
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+ <GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1,
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+ GPOEN_SYS_PWM0_CHANNEL1, GPI_NONE)>;
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+ bias-disable;
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+ drive-strength = <12>;
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+ input-disable;
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+ input-schmitt-disable;
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+ slew-rate = <0>;
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+ };
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+ };
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+
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+ tdm0_pins: tdm0-pins {
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+ tdm0-pins-tx {
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+ pinmux = <GPIOMUX(44, GPOUT_SYS_TDM_TXD,
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+ GPOEN_ENABLE,
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+ GPI_NONE)>;
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+ bias-pull-up;
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+ drive-strength = <2>;
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+ input-disable;
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+ input-schmitt-disable;
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+ slew-rate = <0>;
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+ };
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+
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+ tdm0-pins-rx {
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+ pinmux = <GPIOMUX(61, GPOUT_HIGH,
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+ GPOEN_DISABLE,
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+ GPI_SYS_TDM_RXD)>;
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+ input-enable;
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+ };
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+
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+ tdm0-pins-sync {
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+ pinmux = <GPIOMUX(63, GPOUT_HIGH,
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+ GPOEN_DISABLE,
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+ GPI_SYS_TDM_SYNC)>;
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+ input-enable;
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+ };
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+
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+ tdm0-pins-pcmclk {
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+ pinmux = <GPIOMUX(38, GPOUT_HIGH,
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+ GPOEN_DISABLE,
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+ GPI_SYS_TDM_CLK)>;
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+ input-enable;
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+ };
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+ };
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+
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uart0_pins: uart0-0 {
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tx-pins {
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pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
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@@ -242,8 +553,35 @@
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};
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};
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+&tdm {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&tdm0_pins>;
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+ status = "okay";
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+};
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+
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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+
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+&usb0 {
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+ dr_mode = "peripheral";
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+ status = "okay";
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+};
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+
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+&U74_1 {
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+ cpu-supply = <&vdd_cpu>;
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+};
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+
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+&U74_2 {
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+ cpu-supply = <&vdd_cpu>;
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+};
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+
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+&U74_3 {
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+ cpu-supply = <&vdd_cpu>;
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+};
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+
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+&U74_4 {
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+ cpu-supply = <&vdd_cpu>;
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+};
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--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
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+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
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@@ -6,6 +6,7 @@
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/dts-v1/;
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#include <dt-bindings/clock/starfive,jh7110-crg.h>
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+#include <dt-bindings/power/starfive,jh7110-pmu.h>
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#include <dt-bindings/reset/starfive,jh7110-crg.h>
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/ {
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@@ -53,6 +54,9 @@
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next-level-cache = <&ccache>;
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riscv,isa = "rv64imafdc_zba_zbb";
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tlb-split;
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+ operating-points-v2 = <&cpu_opp>;
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+ clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
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+ clock-names = "cpu";
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cpu1_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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@@ -79,6 +83,9 @@
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next-level-cache = <&ccache>;
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riscv,isa = "rv64imafdc_zba_zbb";
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tlb-split;
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+ operating-points-v2 = <&cpu_opp>;
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+ clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
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+ clock-names = "cpu";
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cpu2_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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@@ -105,6 +112,9 @@
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next-level-cache = <&ccache>;
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riscv,isa = "rv64imafdc_zba_zbb";
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tlb-split;
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+ operating-points-v2 = <&cpu_opp>;
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+ clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
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+ clock-names = "cpu";
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cpu3_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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@@ -131,6 +141,9 @@
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next-level-cache = <&ccache>;
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riscv,isa = "rv64imafdc_zba_zbb";
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tlb-split;
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+ operating-points-v2 = <&cpu_opp>;
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+ clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
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+ clock-names = "cpu";
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cpu4_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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@@ -164,6 +177,33 @@
|
|
};
|
|
};
|
|
|
|
+ cpu_opp: opp-table-0 {
|
|
+ compatible = "operating-points-v2";
|
|
+ opp-shared;
|
|
+ opp-375000000 {
|
|
+ opp-hz = /bits/ 64 <375000000>;
|
|
+ opp-microvolt = <800000>;
|
|
+ };
|
|
+ opp-500000000 {
|
|
+ opp-hz = /bits/ 64 <500000000>;
|
|
+ opp-microvolt = <800000>;
|
|
+ };
|
|
+ opp-750000000 {
|
|
+ opp-hz = /bits/ 64 <750000000>;
|
|
+ opp-microvolt = <800000>;
|
|
+ };
|
|
+ opp-1500000000 {
|
|
+ opp-hz = /bits/ 64 <1500000000>;
|
|
+ opp-microvolt = <1040000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dvp_clk: dvp-clock {
|
|
+ compatible = "fixed-clock";
|
|
+ clock-output-names = "dvp_clk";
|
|
+ #clock-cells = <0>;
|
|
+ };
|
|
+
|
|
gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
|
|
compatible = "fixed-clock";
|
|
clock-output-names = "gmac0_rgmii_rxin";
|
|
@@ -188,6 +228,12 @@
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#clock-cells = <0>;
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|
};
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|
|
|
+ hdmitx0_pixelclk: hdmitx0-pixel-clock {
|
|
+ compatible = "fixed-clock";
|
|
+ clock-output-names = "hdmitx0_pixelclk";
|
|
+ #clock-cells = <0>;
|
|
+ };
|
|
+
|
|
i2srx_bclk_ext: i2srx-bclk-ext-clock {
|
|
compatible = "fixed-clock";
|
|
clock-output-names = "i2srx_bclk_ext";
|
|
@@ -360,6 +406,99 @@
|
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status = "disabled";
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|
};
|
|
|
|
+ tdm: tdm@10090000 {
|
|
+ compatible = "starfive,jh7110-tdm";
|
|
+ reg = <0x0 0x10090000 0x0 0x1000>;
|
|
+ clocks = <&syscrg JH7110_SYSCLK_TDM_AHB>,
|
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+ <&syscrg JH7110_SYSCLK_TDM_APB>,
|
|
+ <&syscrg JH7110_SYSCLK_TDM_INTERNAL>,
|
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+ <&syscrg JH7110_SYSCLK_TDM_TDM>,
|
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+ <&syscrg JH7110_SYSCLK_MCLK_INNER>,
|
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+ <&tdm_ext>;
|
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+ clock-names = "tdm_ahb", "tdm_apb",
|
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+ "tdm_internal", "tdm",
|
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+ "mclk_inner", "tdm_ext";
|
|
+ resets = <&syscrg JH7110_SYSRST_TDM_AHB>,
|
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+ <&syscrg JH7110_SYSRST_TDM_APB>,
|
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+ <&syscrg JH7110_SYSRST_TDM_CORE>;
|
|
+ dmas = <&dma 20>, <&dma 21>;
|
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+ dma-names = "rx","tx";
|
|
+ #sound-dai-cells = <0>;
|
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+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usb0: usb@10100000 {
|
|
+ compatible = "starfive,jh7110-usb";
|
|
+ ranges = <0x0 0x0 0x10100000 0x100000>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ starfive,stg-syscon = <&stg_syscon 0x4>;
|
|
+ clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>,
|
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+ <&stgcrg JH7110_STGCLK_USB0_STB>,
|
|
+ <&stgcrg JH7110_STGCLK_USB0_APB>,
|
|
+ <&stgcrg JH7110_STGCLK_USB0_AXI>,
|
|
+ <&stgcrg JH7110_STGCLK_USB0_UTMI_APB>;
|
|
+ clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
|
|
+ resets = <&stgcrg JH7110_STGRST_USB0_PWRUP>,
|
|
+ <&stgcrg JH7110_STGRST_USB0_APB>,
|
|
+ <&stgcrg JH7110_STGRST_USB0_AXI>,
|
|
+ <&stgcrg JH7110_STGRST_USB0_UTMI_APB>;
|
|
+ reset-names = "pwrup", "apb", "axi", "utmi_apb";
|
|
+ status = "disabled";
|
|
+
|
|
+ usb_cdns3: usb@0 {
|
|
+ compatible = "cdns,usb3";
|
|
+ reg = <0x0 0x10000>,
|
|
+ <0x10000 0x10000>,
|
|
+ <0x20000 0x10000>;
|
|
+ reg-names = "otg", "xhci", "dev";
|
|
+ interrupts = <100>, <108>, <110>;
|
|
+ interrupt-names = "host", "peripheral", "otg";
|
|
+ phys = <&usbphy0>;
|
|
+ phy-names = "cdns3,usb2-phy";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usbphy0: phy@10200000 {
|
|
+ compatible = "starfive,jh7110-usb-phy";
|
|
+ reg = <0x0 0x10200000 0x0 0x10000>;
|
|
+ clocks = <&syscrg JH7110_SYSCLK_USB_125M>,
|
|
+ <&stgcrg JH7110_STGCLK_USB0_APP_125>;
|
|
+ clock-names = "125m", "app_125m";
|
|
+ #phy-cells = <0>;
|
|
+ };
|
|
+
|
|
+ pciephy0: phy@10210000 {
|
|
+ compatible = "starfive,jh7110-pcie-phy";
|
|
+ reg = <0x0 0x10210000 0x0 0x10000>;
|
|
+ #phy-cells = <0>;
|
|
+ };
|
|
+
|
|
+ pciephy1: phy@10220000 {
|
|
+ compatible = "starfive,jh7110-pcie-phy";
|
|
+ reg = <0x0 0x10220000 0x0 0x10000>;
|
|
+ #phy-cells = <0>;
|
|
+ };
|
|
+
|
|
+ stgcrg: clock-controller@10230000 {
|
|
+ compatible = "starfive,jh7110-stgcrg";
|
|
+ reg = <0x0 0x10230000 0x0 0x10000>;
|
|
+ clocks = <&osc>,
|
|
+ <&syscrg JH7110_SYSCLK_HIFI4_CORE>,
|
|
+ <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
|
|
+ <&syscrg JH7110_SYSCLK_USB_125M>,
|
|
+ <&syscrg JH7110_SYSCLK_CPU_BUS>,
|
|
+ <&syscrg JH7110_SYSCLK_HIFI4_AXI>,
|
|
+ <&syscrg JH7110_SYSCLK_NOCSTG_BUS>,
|
|
+ <&syscrg JH7110_SYSCLK_APB_BUS>;
|
|
+ clock-names = "osc", "hifi4_core",
|
|
+ "stg_axiahb", "usb_125m",
|
|
+ "cpu_bus", "hifi4_axi",
|
|
+ "nocstg_bus", "apb_bus";
|
|
+ #clock-cells = <1>;
|
|
+ #reset-cells = <1>;
|
|
+ };
|
|
+
|
|
stg_syscon: syscon@10240000 {
|
|
compatible = "starfive,jh7110-stg-syscon", "syscon";
|
|
reg = <0x0 0x10240000 0x0 0x1000>;
|
|
@@ -452,6 +591,45 @@
|
|
status = "disabled";
|
|
};
|
|
|
|
+ ptc: pwm@120d0000 {
|
|
+ compatible = "starfive,jh7110-pwm";
|
|
+ reg = <0x0 0x120d0000 0x0 0x10000>;
|
|
+ clocks = <&syscrg JH7110_SYSCLK_PWM_APB>;
|
|
+ resets = <&syscrg JH7110_SYSRST_PWM_APB>;
|
|
+ #pwm-cells=<3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ sfctemp: temperature-sensor@120e0000 {
|
|
+ compatible = "starfive,jh7110-temp";
|
|
+ reg = <0x0 0x120e0000 0x0 0x10000>;
|
|
+ clocks = <&syscrg JH7110_SYSCLK_TEMP_CORE>,
|
|
+ <&syscrg JH7110_SYSCLK_TEMP_APB>;
|
|
+ clock-names = "sense", "bus";
|
|
+ resets = <&syscrg JH7110_SYSRST_TEMP_CORE>,
|
|
+ <&syscrg JH7110_SYSRST_TEMP_APB>;
|
|
+ reset-names = "sense", "bus";
|
|
+ #thermal-sensor-cells = <0>;
|
|
+ };
|
|
+
|
|
+ qspi: spi@13010000 {
|
|
+ compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
|
|
+ reg = <0x0 0x13010000 0x0 0x10000
|
|
+ 0x0 0x21000000 0x0 0x400000>;
|
|
+ interrupts = <25>;
|
|
+ clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
|
|
+ <&syscrg JH7110_SYSCLK_QSPI_AHB>,
|
|
+ <&syscrg JH7110_SYSCLK_QSPI_APB>;
|
|
+ clock-names = "qspi-ref", "qspi-ahb", "qspi-apb";
|
|
+ resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
|
|
+ <&syscrg JH7110_SYSRST_QSPI_AHB>,
|
|
+ <&syscrg JH7110_SYSRST_QSPI_REF>;
|
|
+ reset-names = "qspi", "qspi-ocp", "rstc_ref";
|
|
+ cdns,fifo-depth = <256>;
|
|
+ cdns,fifo-width = <4>;
|
|
+ cdns,trigger-address = <0x0>;
|
|
+ };
|
|
+
|
|
syscrg: clock-controller@13020000 {
|
|
compatible = "starfive,jh7110-syscrg";
|
|
reg = <0x0 0x13020000 0x0 0x10000>;
|
|
@@ -496,6 +674,107 @@
|
|
#gpio-cells = <2>;
|
|
};
|
|
|
|
+ timer@13050000 {
|
|
+ compatible = "starfive,jh7110-timer";
|
|
+ reg = <0x0 0x13050000 0x0 0x10000>;
|
|
+ interrupts = <69>, <70>, <71> ,<72>;
|
|
+ clocks = <&syscrg JH7110_SYSCLK_TIMER_APB>,
|
|
+ <&syscrg JH7110_SYSCLK_TIMER0>,
|
|
+ <&syscrg JH7110_SYSCLK_TIMER1>,
|
|
+ <&syscrg JH7110_SYSCLK_TIMER2>,
|
|
+ <&syscrg JH7110_SYSCLK_TIMER3>;
|
|
+ clock-names = "apb", "ch0", "ch1",
|
|
+ "ch2", "ch3";
|
|
+ resets = <&syscrg JH7110_SYSRST_TIMER_APB>,
|
|
+ <&syscrg JH7110_SYSRST_TIMER0>,
|
|
+ <&syscrg JH7110_SYSRST_TIMER1>,
|
|
+ <&syscrg JH7110_SYSRST_TIMER2>,
|
|
+ <&syscrg JH7110_SYSRST_TIMER3>;
|
|
+ reset-names = "apb", "ch0", "ch1",
|
|
+ "ch2", "ch3";
|
|
+ };
|
|
+
|
|
+ watchdog@13070000 {
|
|
+ compatible = "starfive,jh7110-wdt";
|
|
+ reg = <0x0 0x13070000 0x0 0x10000>;
|
|
+ clocks = <&syscrg JH7110_SYSCLK_WDT_APB>,
|
|
+ <&syscrg JH7110_SYSCLK_WDT_CORE>;
|
|
+ clock-names = "apb", "core";
|
|
+ resets = <&syscrg JH7110_SYSRST_WDT_APB>,
|
|
+ <&syscrg JH7110_SYSRST_WDT_CORE>;
|
|
+ };
|
|
+
|
|
+ crypto: crypto@16000000 {
|
|
+ compatible = "starfive,jh7110-crypto";
|
|
+ reg = <0x0 0x16000000 0x0 0x4000>;
|
|
+ clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
|
|
+ <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
|
|
+ clock-names = "hclk", "ahb";
|
|
+ interrupts = <28>;
|
|
+ resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
|
|
+ dmas = <&sdma 1 2>, <&sdma 0 2>;
|
|
+ dma-names = "tx", "rx";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ sdma: dma@16008000 {
|
|
+ compatible = "arm,pl080", "arm,primecell";
|
|
+ arm,primecell-periphid = <0x00041080>;
|
|
+ reg = <0x0 0x16008000 0x0 0x4000>;
|
|
+ interrupts = <29>;
|
|
+ clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
|
|
+ <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
|
|
+ clock-names = "hclk", "apb_pclk";
|
|
+ resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
|
|
+ lli-bus-interface-ahb1;
|
|
+ mem-bus-interface-ahb1;
|
|
+ memcpy-burst-size = <256>;
|
|
+ memcpy-bus-width = <32>;
|
|
+ #dma-cells = <2>;
|
|
+ };
|
|
+
|
|
+ rng: rng@1600c000 {
|
|
+ compatible = "starfive,jh7110-trng";
|
|
+ reg = <0x0 0x1600C000 0x0 0x4000>;
|
|
+ clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
|
|
+ <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
|
|
+ clock-names = "hclk", "ahb";
|
|
+ resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
|
|
+ interrupts = <30>;
|
|
+ };
|
|
+
|
|
+ mmc0: mmc@16010000 {
|
|
+ compatible = "starfive,jh7110-mmc";
|
|
+ reg = <0x0 0x16010000 0x0 0x10000>;
|
|
+ clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
|
|
+ <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
|
|
+ clock-names = "biu","ciu";
|
|
+ resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
|
|
+ reset-names = "reset";
|
|
+ interrupts = <74>;
|
|
+ fifo-depth = <32>;
|
|
+ fifo-watermark-aligned;
|
|
+ data-addr = <0>;
|
|
+ starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ mmc1: mmc@16020000 {
|
|
+ compatible = "starfive,jh7110-mmc";
|
|
+ reg = <0x0 0x16020000 0x0 0x10000>;
|
|
+ clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
|
|
+ <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
|
|
+ clock-names = "biu","ciu";
|
|
+ resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
|
|
+ reset-names = "reset";
|
|
+ interrupts = <75>;
|
|
+ fifo-depth = <32>;
|
|
+ fifo-watermark-aligned;
|
|
+ data-addr = <0>;
|
|
+ starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
gmac0: ethernet@16030000 {
|
|
compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
|
|
reg = <0x0 0x16030000 0x0 0x10000>;
|
|
@@ -558,6 +837,24 @@
|
|
status = "disabled";
|
|
};
|
|
|
|
+ dma: dma-controller@16050000 {
|
|
+ compatible = "starfive,jh7110-axi-dma";
|
|
+ reg = <0x0 0x16050000 0x0 0x10000>;
|
|
+ clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>,
|
|
+ <&stgcrg JH7110_STGCLK_DMA1P_AHB>;
|
|
+ clock-names = "core-clk", "cfgr-clk";
|
|
+ resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>,
|
|
+ <&stgcrg JH7110_STGRST_DMA1P_AHB>;
|
|
+ interrupts = <73>;
|
|
+ #dma-cells = <1>;
|
|
+ dma-channels = <4>;
|
|
+ snps,dma-masters = <1>;
|
|
+ snps,data-width = <3>;
|
|
+ snps,block-size = <65536 65536 65536 65536>;
|
|
+ snps,priority = <0 1 2 3>;
|
|
+ snps,axi-max-burst-len = <16>;
|
|
+ };
|
|
+
|
|
aoncrg: clock-controller@17000000 {
|
|
compatible = "starfive,jh7110-aoncrg";
|
|
reg = <0x0 0x17000000 0x0 0x10000>;
|
|
@@ -576,8 +873,9 @@
|
|
};
|
|
|
|
aon_syscon: syscon@17010000 {
|
|
- compatible = "starfive,jh7110-aon-syscon", "syscon", "simple-mfd";
|
|
+ compatible = "starfive,jh7110-aon-syscon", "syscon";
|
|
reg = <0x0 0x17010000 0x0 0x1000>;
|
|
+ #power-domain-cells = <1>;
|
|
};
|
|
|
|
aongpio: pinctrl@17020000 {
|
|
@@ -590,5 +888,211 @@
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
};
|
|
+
|
|
+ pwrc: power-controller@17030000 {
|
|
+ compatible = "starfive,jh7110-pmu";
|
|
+ reg = <0x0 0x17030000 0x0 0x10000>;
|
|
+ interrupts = <111>;
|
|
+ #power-domain-cells = <1>;
|
|
+ };
|
|
+
|
|
+ csi2rx: csi-bridge@19800000 {
|
|
+ compatible = "starfive,jh7110-csi2rx";
|
|
+ reg = <0x0 0x19800000 0x0 0x10000>;
|
|
+ clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>,
|
|
+ <&ispcrg JH7110_ISPCLK_VIN_APB>,
|
|
+ <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF0>,
|
|
+ <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF1>,
|
|
+ <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF2>,
|
|
+ <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF3>;
|
|
+ clock-names = "sys_clk", "p_clk",
|
|
+ "pixel_if0_clk", "pixel_if1_clk",
|
|
+ "pixel_if2_clk", "pixel_if3_clk";
|
|
+ resets = <&ispcrg JH7110_ISPRST_VIN_SYS>,
|
|
+ <&ispcrg JH7110_ISPRST_VIN_APB>,
|
|
+ <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF0>,
|
|
+ <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF1>,
|
|
+ <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF2>,
|
|
+ <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF3>;
|
|
+ reset-names = "sys", "reg_bank",
|
|
+ "pixel_if0", "pixel_if1",
|
|
+ "pixel_if2", "pixel_if3";
|
|
+ phys = <&csi_phy>;
|
|
+ phy-names = "dphy";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ ispcrg: clock-controller@19810000 {
|
|
+ compatible = "starfive,jh7110-ispcrg";
|
|
+ reg = <0x0 0x19810000 0x0 0x10000>;
|
|
+ clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
|
|
+ <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>,
|
|
+ <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>,
|
|
+ <&dvp_clk>;
|
|
+ clock-names = "isp_top_core", "isp_top_axi",
|
|
+ "noc_bus_isp_axi", "dvp_clk";
|
|
+ resets = <&syscrg JH7110_SYSRST_ISP_TOP>,
|
|
+ <&syscrg JH7110_SYSRST_ISP_TOP_AXI>,
|
|
+ <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>;
|
|
+ #clock-cells = <1>;
|
|
+ #reset-cells = <1>;
|
|
+ power-domains = <&pwrc JH7110_PD_ISP>;
|
|
+ };
|
|
+
|
|
+ csi_phy: phy@19820000 {
|
|
+ compatible = "starfive,jh7110-dphy-rx";
|
|
+ reg = <0x0 0x19820000 0x0 0x10000>;
|
|
+ clocks = <&ispcrg JH7110_ISPCLK_M31DPHY_CFG_IN>,
|
|
+ <&ispcrg JH7110_ISPCLK_M31DPHY_REF_IN>,
|
|
+ <&ispcrg JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0>;
|
|
+ clock-names = "cfg", "ref", "tx";
|
|
+ resets = <&ispcrg JH7110_ISPRST_M31DPHY_HW>,
|
|
+ <&ispcrg JH7110_ISPRST_M31DPHY_B09_AON>;
|
|
+ power-domains = <&aon_syscon JH7110_PD_DPHY_RX>;
|
|
+ #phy-cells = <0>;
|
|
+ };
|
|
+
|
|
+ stfcamss: camss@19840000 {
|
|
+ compatible = "starfive,jh7110-camss";
|
|
+ reg = <0x0 0x19840000 0x0 0x10000>,
|
|
+ <0x0 0x19870000 0x0 0x30000>;
|
|
+ reg-names = "syscon", "isp";
|
|
+ clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>,
|
|
+ <&ispcrg JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C>,
|
|
+ <&ispcrg JH7110_ISPCLK_DVP_INV>,
|
|
+ <&ispcrg JH7110_ISPCLK_VIN_P_AXI_WR>,
|
|
+ <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>,
|
|
+ <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
|
|
+ <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>;
|
|
+ clock-names = "clk_apb_func",
|
|
+ "clk_wrapper_clk_c",
|
|
+ "clk_dvp_inv",
|
|
+ "clk_axiwr",
|
|
+ "clk_mipi_rx0_pxl",
|
|
+ "clk_ispcore_2x",
|
|
+ "clk_isp_axi";
|
|
+ resets = <&ispcrg JH7110_ISPRST_ISPV2_TOP_WRAPPER_P>,
|
|
+ <&ispcrg JH7110_ISPRST_ISPV2_TOP_WRAPPER_C>,
|
|
+ <&ispcrg JH7110_ISPRST_VIN_P_AXI_RD>,
|
|
+ <&ispcrg JH7110_ISPRST_VIN_P_AXI_WR>,
|
|
+ <&syscrg JH7110_SYSRST_ISP_TOP>,
|
|
+ <&syscrg JH7110_SYSRST_ISP_TOP_AXI>;
|
|
+ reset-names = "rst_wrapper_p",
|
|
+ "rst_wrapper_c",
|
|
+ "rst_axird",
|
|
+ "rst_axiwr",
|
|
+ "rst_isp_top_n",
|
|
+ "rst_isp_top_axi";
|
|
+ power-domains = <&pwrc JH7110_PD_ISP>;
|
|
+ /* irq nr: vin, isp, isp_csi, isp_csiline */
|
|
+ interrupts = <92>, <87>, <90>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ voutcrg: clock-controller@295c0000 {
|
|
+ compatible = "starfive,jh7110-voutcrg";
|
|
+ reg = <0x0 0x295c0000 0x0 0x10000>;
|
|
+ clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
|
|
+ <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
|
|
+ <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
|
|
+ <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
|
|
+ <&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
|
|
+ <&hdmitx0_pixelclk>;
|
|
+ clock-names = "vout_src", "vout_top_ahb",
|
|
+ "vout_top_axi", "vout_top_hdmitx0_mclk",
|
|
+ "i2stx0_bclk", "hdmitx0_pixelclk";
|
|
+ resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
|
|
+ #clock-cells = <1>;
|
|
+ #reset-cells = <1>;
|
|
+ power-domains = <&pwrc JH7110_PD_VOUT>;
|
|
+ };
|
|
+
|
|
+ pcie0: pcie@2B000000 {
|
|
+ compatible = "starfive,jh7110-pcie";
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ #interrupt-cells = <1>;
|
|
+ reg = <0x0 0x2B000000 0x0 0x1000000
|
|
+ 0x9 0x40000000 0x0 0x10000000>;
|
|
+ reg-names = "reg", "config";
|
|
+ device_type = "pci";
|
|
+ starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>;
|
|
+ bus-range = <0x0 0xff>;
|
|
+ ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
|
|
+ <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
|
|
+ interrupts = <56>;
|
|
+ interrupt-parent = <&plic>;
|
|
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
|
+ interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
|
|
+ <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
|
|
+ <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
|
|
+ <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
|
|
+ msi-parent = <&pcie0>;
|
|
+ msi-controller;
|
|
+ clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
|
|
+ <&stgcrg JH7110_STGCLK_PCIE0_TL>,
|
|
+ <&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>,
|
|
+ <&stgcrg JH7110_STGCLK_PCIE0_APB>;
|
|
+ clock-names = "noc", "tl", "axi_mst0", "apb";
|
|
+ resets = <&stgcrg JH7110_STGRST_PCIE0_AXI_MST0>,
|
|
+ <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV0>,
|
|
+ <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV>,
|
|
+ <&stgcrg JH7110_STGRST_PCIE0_BRG>,
|
|
+ <&stgcrg JH7110_STGRST_PCIE0_CORE>,
|
|
+ <&stgcrg JH7110_STGRST_PCIE0_APB>;
|
|
+ reset-names = "mst0", "slv0", "slv", "brg",
|
|
+ "core", "apb";
|
|
+ status = "disabled";
|
|
+
|
|
+ pcie_intc0: interrupt-controller {
|
|
+ #address-cells = <0>;
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-controller;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pcie1: pcie@2C000000 {
|
|
+ compatible = "starfive,jh7110-pcie";
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ #interrupt-cells = <1>;
|
|
+ reg = <0x0 0x2C000000 0x0 0x1000000
|
|
+ 0x9 0xc0000000 0x0 0x10000000>;
|
|
+ reg-names = "reg", "config";
|
|
+ device_type = "pci";
|
|
+ starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0 0x368>;
|
|
+ bus-range = <0x0 0xff>;
|
|
+ ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>,
|
|
+ <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
|
|
+ interrupts = <57>;
|
|
+ interrupt-parent = <&plic>;
|
|
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
|
+ interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc1 0x1>,
|
|
+ <0x0 0x0 0x0 0x2 &pcie_intc1 0x2>,
|
|
+ <0x0 0x0 0x0 0x3 &pcie_intc1 0x3>,
|
|
+ <0x0 0x0 0x0 0x4 &pcie_intc1 0x4>;
|
|
+ msi-parent = <&pcie1>;
|
|
+ msi-controller;
|
|
+ clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
|
|
+ <&stgcrg JH7110_STGCLK_PCIE1_TL>,
|
|
+ <&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>,
|
|
+ <&stgcrg JH7110_STGCLK_PCIE1_APB>;
|
|
+ clock-names = "noc", "tl", "axi_mst0", "apb";
|
|
+ resets = <&stgcrg JH7110_STGRST_PCIE1_AXI_MST0>,
|
|
+ <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV0>,
|
|
+ <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV>,
|
|
+ <&stgcrg JH7110_STGRST_PCIE1_BRG>,
|
|
+ <&stgcrg JH7110_STGRST_PCIE1_CORE>,
|
|
+ <&stgcrg JH7110_STGRST_PCIE1_APB>;
|
|
+ reset-names = "mst0", "slv0", "slv", "brg",
|
|
+ "core", "apb";
|
|
+ status = "disabled";
|
|
+
|
|
+ pcie_intc1: interrupt-controller {
|
|
+ #address-cells = <0>;
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-controller;
|
|
+ };
|
|
+ };
|
|
};
|
|
};
|