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4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
177 lines
5.4 KiB
Diff
177 lines
5.4 KiB
Diff
From cd833f484009f37be57a2aa09257af6e8c1b25b6 Mon Sep 17 00:00:00 2001
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From: Emil Renner Berthing <kernel@esmil.dk>
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Date: Sat, 1 Apr 2023 19:19:14 +0800
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Subject: [PATCH 002/122] dt-bindings: clock: Add StarFive JH7110 always-on
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clock and reset generator
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Add bindings for the always-on clock and reset generator (AONCRG) on the
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JH7110 RISC-V SoC by StarFive Ltd.
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Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
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Reviewed-by: Rob Herring <robh@kernel.org>
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Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
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Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
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Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
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Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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---
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.../clock/starfive,jh7110-aoncrg.yaml | 107 ++++++++++++++++++
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.../dt-bindings/clock/starfive,jh7110-crg.h | 18 +++
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.../dt-bindings/reset/starfive,jh7110-crg.h | 12 ++
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3 files changed, 137 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
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@@ -0,0 +1,107 @@
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+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: StarFive JH7110 Always-On Clock and Reset Generator
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+
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+maintainers:
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+ - Emil Renner Berthing <kernel@esmil.dk>
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+
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+properties:
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+ compatible:
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+ const: starfive,jh7110-aoncrg
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+
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+ reg:
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+ maxItems: 1
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+
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+ clocks:
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+ oneOf:
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+ - items:
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+ - description: Main Oscillator (24 MHz)
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+ - description: GMAC0 RMII reference or GMAC0 RGMII RX
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+ - description: STG AXI/AHB
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+ - description: APB Bus
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+ - description: GMAC0 GTX
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+
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+ - items:
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+ - description: Main Oscillator (24 MHz)
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+ - description: GMAC0 RMII reference or GMAC0 RGMII RX
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+ - description: STG AXI/AHB or GMAC0 RGMII RX
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+ - description: APB Bus or STG AXI/AHB
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+ - description: GMAC0 GTX or APB Bus
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+ - description: RTC Oscillator (32.768 kHz) or GMAC0 GTX
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+
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+ - items:
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+ - description: Main Oscillator (24 MHz)
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+ - description: GMAC0 RMII reference
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+ - description: GMAC0 RGMII RX
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+ - description: STG AXI/AHB
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+ - description: APB Bus
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+ - description: GMAC0 GTX
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+ - description: RTC Oscillator (32.768 kHz)
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+
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+ clock-names:
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+ oneOf:
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+ - minItems: 5
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+ items:
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+ - const: osc
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+ - enum:
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+ - gmac0_rmii_refin
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+ - gmac0_rgmii_rxin
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+ - const: stg_axiahb
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+ - const: apb_bus
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+ - const: gmac0_gtxclk
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+ - const: rtc_osc
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+
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+ - minItems: 6
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+ items:
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+ - const: osc
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+ - const: gmac0_rmii_refin
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+ - const: gmac0_rgmii_rxin
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+ - const: stg_axiahb
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+ - const: apb_bus
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+ - const: gmac0_gtxclk
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+ - const: rtc_osc
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+
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+ '#clock-cells':
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+ const: 1
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+ description:
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+ See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
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+
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+ '#reset-cells':
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+ const: 1
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+ description:
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+ See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
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+
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+required:
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+ - compatible
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+ - reg
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+ - clocks
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+ - clock-names
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+ - '#clock-cells'
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+ - '#reset-cells'
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ #include <dt-bindings/clock/starfive,jh7110-crg.h>
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+
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+ clock-controller@17000000 {
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+ compatible = "starfive,jh7110-aoncrg";
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+ reg = <0x17000000 0x10000>;
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+ clocks = <&osc>, <&gmac0_rmii_refin>,
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+ <&gmac0_rgmii_rxin>,
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+ <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
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+ <&syscrg JH7110_SYSCLK_APB_BUS>,
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+ <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,
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+ <&rtc_osc>;
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+ clock-names = "osc", "gmac0_rmii_refin",
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+ "gmac0_rgmii_rxin", "stg_axiahb",
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+ "apb_bus", "gmac0_gtxclk",
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+ "rtc_osc";
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ };
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--- a/include/dt-bindings/clock/starfive,jh7110-crg.h
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+++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
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@@ -200,4 +200,22 @@
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#define JH7110_SYSCLK_END 190
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+/* AONCRG clocks */
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+#define JH7110_AONCLK_OSC_DIV4 0
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+#define JH7110_AONCLK_APB_FUNC 1
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+#define JH7110_AONCLK_GMAC0_AHB 2
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+#define JH7110_AONCLK_GMAC0_AXI 3
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+#define JH7110_AONCLK_GMAC0_RMII_RTX 4
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+#define JH7110_AONCLK_GMAC0_TX 5
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+#define JH7110_AONCLK_GMAC0_TX_INV 6
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+#define JH7110_AONCLK_GMAC0_RX 7
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+#define JH7110_AONCLK_GMAC0_RX_INV 8
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+#define JH7110_AONCLK_OTPC_APB 9
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+#define JH7110_AONCLK_RTC_APB 10
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+#define JH7110_AONCLK_RTC_INTERNAL 11
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+#define JH7110_AONCLK_RTC_32K 12
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+#define JH7110_AONCLK_RTC_CAL 13
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+
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+#define JH7110_AONCLK_END 14
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+
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#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */
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--- a/include/dt-bindings/reset/starfive,jh7110-crg.h
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+++ b/include/dt-bindings/reset/starfive,jh7110-crg.h
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@@ -139,4 +139,16 @@
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#define JH7110_SYSRST_END 126
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+/* AONCRG resets */
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+#define JH7110_AONRST_GMAC0_AXI 0
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+#define JH7110_AONRST_GMAC0_AHB 1
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+#define JH7110_AONRST_IOMUX 2
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+#define JH7110_AONRST_PMU_APB 3
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+#define JH7110_AONRST_PMU_WKUP 4
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+#define JH7110_AONRST_RTC_APB 5
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+#define JH7110_AONRST_RTC_CAL 6
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+#define JH7110_AONRST_RTC_32K 7
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+
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+#define JH7110_AONRST_END 8
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+
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#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */
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