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ab7cabd09d
Compile-tested on: ramips/mt7621, x86/64. Run-tested on: ramips/mt7621. Signed-off-by: Stijn Segers <foss@volatilesystems.org>
97 lines
2.3 KiB
Diff
97 lines
2.3 KiB
Diff
From 0a84c72d1c606129b8af670cbcc73be4168ab753 Mon Sep 17 00:00:00 2001
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From: Sean Wang <sean.wang@mediatek.com>
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Date: Fri, 29 Dec 2017 10:36:37 +0800
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Subject: [PATCH 217/224] arm64: dts: mt7622: add flash related device nodes
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add nodes for NOR flash, parallel Nand flash with error correction code
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support.
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Signed-off-by: Sean Wang <sean.wang@mediatek.com>
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Cc: RogerCC Lin <rogercc.lin@mediatek.com>
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Cc: Guochun Mao <guochun.mao@mediatek.com>
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---
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arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 21 +++++++++++++++++
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arch/arm64/boot/dts/mediatek/mt7622.dtsi | 34 ++++++++++++++++++++++++++++
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2 files changed, 55 insertions(+)
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--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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@@ -235,6 +235,10 @@
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};
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};
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+&bch {
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+ status = "disabled";
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+};
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+
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&btif {
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status = "okay";
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};
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@@ -257,6 +261,23 @@
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status = "okay";
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};
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+&nandc {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <¶llel_nand_pins>;
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+ status = "disabled";
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+};
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+
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+&nor_flash {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&spi_nor_pins>;
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+ status = "disabled";
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+
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+ flash@0 {
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+ compatible = "jedec,spi-nor";
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+ reg = <0>;
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+ };
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+};
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+
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&pwm {
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pinctrl-names = "default";
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pinctrl-0 = <&pwm7_pins>;
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--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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@@ -468,6 +468,40 @@
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status = "disabled";
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};
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+ nandc: nfi@1100d000 {
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+ compatible = "mediatek,mt7622-nfc";
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+ reg = <0 0x1100D000 0 0x1000>;
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+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&pericfg CLK_PERI_NFI_PD>,
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+ <&pericfg CLK_PERI_SNFI_PD>;
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+ clock-names = "nfi_clk", "pad_clk";
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+ ecc-engine = <&bch>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ bch: ecc@1100e000 {
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+ compatible = "mediatek,mt7622-ecc";
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+ reg = <0 0x1100e000 0 0x1000>;
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+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&pericfg CLK_PERI_NFIECC_PD>;
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+ clock-names = "nfiecc_clk";
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+ status = "disabled";
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+ };
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+
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+ nor_flash: spi@11014000 {
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+ compatible = "mediatek,mt7622-nor",
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+ "mediatek,mt8173-nor";
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+ reg = <0 0x11014000 0 0xe0>;
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+ clocks = <&pericfg CLK_PERI_FLASH_PD>,
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+ <&topckgen CLK_TOP_FLASH_SEL>;
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+ clock-names = "spi", "sf";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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spi1: spi@11016000 {
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compatible = "mediatek,mt7622-spi";
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reg = <0 0x11016000 0 0x100>;
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