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6bc9a6d0a8
Build and boot tested on the following hardware: * GW54xx * GW53xx * GW52xx * GW51xx Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Pushpal Sidhu <psidhu@gateworks.com> SVN-Revision: 47331
124 lines
2.6 KiB
C
124 lines
2.6 KiB
C
/*
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* drivers/net/phy/mv88e6176.h
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*
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* Driver for Marvell Switch
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*
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* Author: Tim Harvey
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*
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* Copyright (c) 2014 Tim Harvey <tharvey@gateworks.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#ifndef _GW16083_H_
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#define _GW16083_H_
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#define MII_MARVELL_PHY_PAGE 22
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/*
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* I2C Addresses
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*/
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#define GW16083_I2C_ADDR_SFP1 0x50
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#define GW16083_I2C_ADDR_SFP2 0x51
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#define GW16083_I2C_ADDR_EEPROM 0x52
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#define GW16083_I2C_ADDR_PCA9543 0x70
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/*
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* MV88E1111 PHY Registers
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*/
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enum {
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MII_M1111_PHY_CONTROL = 0,
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MII_M1111_PHY_STATUS = 1,
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MII_M1111_PHY_IDENT0 = 2,
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MII_M1111_PHY_IDENT1 = 3,
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MII_M1111_PHY_EXT_CR = 20,
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MII_M1111_PHY_LED_CONTROL = 24,
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MII_M1111_PHY_EXT_SR = 27,
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};
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#define MII_M1111_PHY_ID_MASK 0xfffffff0
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#define MII_M1111_PHY_ID 0x01410cc0
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#define MII_M1111_PHY_CONTROL_RESET (1 << 15)
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#define MII_M1111_PHY_LED_DIRECT 0x4100
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#define MII_M1111_PHY_LED_PULSE_STR 0x4111
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#define MII_M1111_PHY_LED_COMBINE 0x411c
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#define MII_M1111_RX_DELAY 0x80
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#define MII_M1111_TX_DELAY 0x2
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/*
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* MV88E6176 Switch Registers
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*/
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/* PHY Addrs */
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#define MV_BASE 0x10
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#define MV_GLOBAL1 0x1b
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#define MV_GLOBAL2 0x1c
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#define MV_GLOBAL3 0x1d
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/* Global2 Registers */
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enum {
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MV_SMI_PHY_COMMAND = 0x18,
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MV_SMI_PHY_DATA = 0x19,
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MV_SCRATCH_MISC = 0x1A,
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};
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/* Scratch And Misc Reg offsets */
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enum {
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MV_GPIO_MODE = 0x60,
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MV_GPIO_DIR = 0x62,
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MV_GPIO_DATA = 0x64,
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MV_GPIO76_CNTL = 0x6B,
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MV_GPIO54_CNTL = 0x6A,
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MV_GPIO32_CNTL = 0x69,
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MV_GPIO10_CNTL = 0x68,
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MV_CONFIG0 = 0x70,
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MV_CONFIG1 = 0x71,
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MV_CONFIG2 = 0x72,
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MV_CONFIG3 = 0x73,
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};
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/* PHY Registers */
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enum {
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MV_PHY_CONTROL = 0x00,
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MV_PHY_STATUS = 0x01,
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MV_PHY_IDENT0 = 0x02,
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MV_PHY_IDENT1 = 0x03,
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MV_PHY_ANEG = 0x04,
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MV_PHY_LINK_ABILITY = 0x05,
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MV_PHY_ANEG_EXPAND = 0x06,
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MV_PHY_XMIT_NEXTP = 0x07,
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MV_PHY_LINK_NEXTP = 0x08,
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MV_PHY_CONTROL1 = 0x10,
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MV_PHY_STATUS1 = 0x11,
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MV_PHY_INTR_EN = 0x12,
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};
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/* Port Registers */
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enum {
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MV_PORT_STATUS = 0x00,
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MV_PORT_PHYS_CONTROL = 0x01,
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MV_PORT_IDENT = 0x03,
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MV_PORT_CONTROL = 0x04,
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MV_PORT_VLANMAP = 0x06,
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MV_PORT_ASSOC = 0x0b,
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MV_PORT_RXCOUNT = 0x10,
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MV_PORT_TXCOUNT = 0x11,
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};
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#define SMIBUSY (1<<15)
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#define SMIMODE22 (1<<12)
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#define SMIOP_READ (2<<10)
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#define SMIOP_WRITE (1<<10)
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#define DEVADDR 5
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#define REGADDR 0
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#define MV_IDENT_MASK 0x0000fff0
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#define MV_IDENT_VALUE 0x00001760
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#endif /* _GW16083_H_ */
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