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4089df4f4b
Refreshed all patches. This bump contains upstream commits which seem to avoid (not properly fix) the errors as seen in FS#2305 and FS#2297 Altered patches: - 403-net-mvneta-convert-to-phylink.patch - 410-sfp-hack-allow-marvell-10G-phy-support-to-use-SFP.patch Compile-tested on: ar71xx, cns3xxx, imx6, mvebu, x86_64 Runtime-tested on: ar71xx, cns3xxx, imx6, x86_64 Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
234 lines
6.1 KiB
Diff
234 lines
6.1 KiB
Diff
From 3765b1f79593a0a9098ed15e48074c95403a53ee Mon Sep 17 00:00:00 2001
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From: John Crispin <john@phrozen.org>
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Date: Sat, 23 Jun 2018 15:05:08 +0200
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Subject: [PATCH 27/33] MIPS: ath79: drop legacy IRQ code
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With the target now being fully OF based, we can drop the legacy IRQ code.
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All IRQs are now handled via the new irqchip drivers.
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Signed-off-by: John Crispin <john@phrozen.org>
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---
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arch/mips/ath79/Makefile | 2 +-
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arch/mips/ath79/irq.c | 169 -------------------------------
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arch/mips/ath79/setup.c | 6 ++
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arch/mips/include/asm/mach-ath79/ath79.h | 4 -
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4 files changed, 7 insertions(+), 174 deletions(-)
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delete mode 100644 arch/mips/ath79/irq.c
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--- a/arch/mips/ath79/Makefile
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+++ b/arch/mips/ath79/Makefile
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@@ -8,7 +8,7 @@
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# under the terms of the GNU General Public License version 2 as published
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# by the Free Software Foundation.
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-obj-y := prom.o setup.o irq.o common.o clock.o
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+obj-y := prom.o setup.o common.o clock.o
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obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
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obj-$(CONFIG_PCI) += pci.o
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--- a/arch/mips/ath79/irq.c
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+++ /dev/null
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@@ -1,169 +0,0 @@
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-/*
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- * Atheros AR71xx/AR724x/AR913x specific interrupt handling
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- *
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- * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
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- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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- *
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- * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms of the GNU General Public License version 2 as published
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- * by the Free Software Foundation.
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- */
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-
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-#include <linux/kernel.h>
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-#include <linux/init.h>
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-#include <linux/interrupt.h>
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-#include <linux/irqchip.h>
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-#include <linux/of_irq.h>
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-
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-#include <asm/irq_cpu.h>
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-#include <asm/mipsregs.h>
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-
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-#include <asm/mach-ath79/ath79.h>
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-#include <asm/mach-ath79/ar71xx_regs.h>
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-#include "common.h"
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-#include "machtypes.h"
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-
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-
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-static void ar934x_ip2_irq_dispatch(struct irq_desc *desc)
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-{
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- u32 status;
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-
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- status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
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-
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- if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) {
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- ath79_ddr_wb_flush(3);
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- generic_handle_irq(ATH79_IP2_IRQ(0));
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- } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) {
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- ath79_ddr_wb_flush(4);
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- generic_handle_irq(ATH79_IP2_IRQ(1));
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- } else {
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- spurious_interrupt();
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- }
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-}
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-
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-static void ar934x_ip2_irq_init(void)
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-{
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- int i;
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-
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- for (i = ATH79_IP2_IRQ_BASE;
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- i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
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- irq_set_chip_and_handler(i, &dummy_irq_chip,
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- handle_level_irq);
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-
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- irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
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-}
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-
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-static void qca955x_ip2_irq_dispatch(struct irq_desc *desc)
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-{
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- u32 status;
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-
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- status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
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- status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL;
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-
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- if (status == 0) {
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- spurious_interrupt();
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- return;
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- }
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-
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- if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) {
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- /* TODO: flush DDR? */
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- generic_handle_irq(ATH79_IP2_IRQ(0));
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- }
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-
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- if (status & QCA955X_EXT_INT_WMAC_ALL) {
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- /* TODO: flush DDR? */
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- generic_handle_irq(ATH79_IP2_IRQ(1));
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- }
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-}
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-
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-static void qca955x_ip3_irq_dispatch(struct irq_desc *desc)
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-{
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- u32 status;
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-
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- status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
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- status &= QCA955X_EXT_INT_PCIE_RC2_ALL |
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- QCA955X_EXT_INT_USB1 |
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- QCA955X_EXT_INT_USB2;
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-
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- if (status == 0) {
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- spurious_interrupt();
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- return;
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- }
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-
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- if (status & QCA955X_EXT_INT_USB1) {
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- /* TODO: flush DDR? */
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- generic_handle_irq(ATH79_IP3_IRQ(0));
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- }
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-
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- if (status & QCA955X_EXT_INT_USB2) {
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- /* TODO: flush DDR? */
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- generic_handle_irq(ATH79_IP3_IRQ(1));
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- }
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-
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- if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) {
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- /* TODO: flush DDR? */
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- generic_handle_irq(ATH79_IP3_IRQ(2));
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- }
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-}
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-
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-static void qca955x_irq_init(void)
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-{
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- int i;
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-
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- for (i = ATH79_IP2_IRQ_BASE;
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- i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
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- irq_set_chip_and_handler(i, &dummy_irq_chip,
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- handle_level_irq);
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-
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- irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
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-
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- for (i = ATH79_IP3_IRQ_BASE;
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- i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
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- irq_set_chip_and_handler(i, &dummy_irq_chip,
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- handle_level_irq);
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-
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- irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
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-}
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-
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-void __init arch_init_irq(void)
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-{
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- unsigned irq_wb_chan2 = -1;
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- unsigned irq_wb_chan3 = -1;
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- bool misc_is_ar71xx;
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-
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- if (mips_machtype == ATH79_MACH_GENERIC_OF) {
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- irqchip_init();
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- return;
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- }
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-
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- if (soc_is_ar71xx() || soc_is_ar724x() ||
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- soc_is_ar913x() || soc_is_ar933x()) {
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- irq_wb_chan2 = 3;
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- irq_wb_chan3 = 2;
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- } else if (soc_is_ar934x()) {
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- irq_wb_chan3 = 2;
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- }
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-
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- ath79_cpu_irq_init(irq_wb_chan2, irq_wb_chan3);
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-
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- if (soc_is_ar71xx() || soc_is_ar913x())
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- misc_is_ar71xx = true;
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- else if (soc_is_ar724x() ||
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- soc_is_ar933x() ||
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- soc_is_ar934x() ||
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- soc_is_qca955x())
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- misc_is_ar71xx = false;
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- else
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- BUG();
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- ath79_misc_irq_init(
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- ath79_reset_base + AR71XX_RESET_REG_MISC_INT_STATUS,
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- ATH79_CPU_IRQ(6), ATH79_MISC_IRQ_BASE, misc_is_ar71xx);
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-
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- if (soc_is_ar934x())
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- ar934x_ip2_irq_init();
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- else if (soc_is_qca955x())
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- qca955x_irq_init();
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-}
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--- a/arch/mips/ath79/setup.c
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+++ b/arch/mips/ath79/setup.c
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@@ -19,6 +19,7 @@
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/of_fdt.h>
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+#include <linux/irqchip.h>
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#include <asm/bootinfo.h>
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#include <asm/idle.h>
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@@ -311,6 +312,11 @@ void __init plat_time_init(void)
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mips_hpt_frequency = cpu_clk_rate / 2;
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}
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+void __init arch_init_irq(void)
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+{
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+ irqchip_init();
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+}
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+
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static int __init ath79_setup(void)
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{
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if (mips_machtype == ATH79_MACH_GENERIC_OF)
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--- a/arch/mips/include/asm/mach-ath79/ath79.h
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+++ b/arch/mips/include/asm/mach-ath79/ath79.h
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@@ -178,8 +178,4 @@ static inline u32 ath79_reset_rr(unsigne
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void ath79_device_reset_set(u32 mask);
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void ath79_device_reset_clear(u32 mask);
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-void ath79_cpu_irq_init(unsigned irq_wb_chan2, unsigned irq_wb_chan3);
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-void ath79_misc_irq_init(void __iomem *regs, int irq,
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- int irq_base, bool is_ar71xx);
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-
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#endif /* __ASM_MACH_ATH79_H */
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