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4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
304 lines
8.2 KiB
Diff
304 lines
8.2 KiB
Diff
From 28518a9637fee6b84464beff9d4308edc3efba72 Mon Sep 17 00:00:00 2001
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From: Jianlong Huang <jianlong.huang@starfivetech.com>
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Date: Thu, 9 Feb 2023 22:36:59 +0800
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Subject: [PATCH 026/122] dt-bindings: pinctrl: Add StarFive JH7110 sys pinctrl
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Add pinctrl bindings for StarFive JH7110 SoC sys pinctrl controller.
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Reviewed-by: Rob Herring <robh@kernel.org>
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Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
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Co-developed-by: Emil Renner Berthing <kernel@esmil.dk>
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Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
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Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
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---
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.../pinctrl/starfive,jh7110-sys-pinctrl.yaml | 142 ++++++++++++++++++
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MAINTAINERS | 6 +-
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.../pinctrl/starfive,jh7110-pinctrl.h | 115 ++++++++++++++
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3 files changed, 261 insertions(+), 2 deletions(-)
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create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml
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create mode 100644 include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml
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@@ -0,0 +1,142 @@
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+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-sys-pinctrl.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: StarFive JH7110 SYS Pin Controller
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+
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+description: |
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+ Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
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+
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+ Out of the SoC's many pins only the ones named PAD_GPIO0 to PAD_GPIO63
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+ can be multiplexed and have configurable bias, drive strength,
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+ schmitt trigger etc.
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+ Some peripherals have their I/O go through the 64 "GPIOs". This also
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+ includes a number of other UARTs, I2Cs, SPIs, PWMs etc.
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+ All these peripherals are connected to all 64 GPIOs such that
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+ any GPIO can be set up to be controlled by any of the peripherals.
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+
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+maintainers:
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+ - Jianlong Huang <jianlong.huang@starfivetech.com>
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+
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+properties:
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+ compatible:
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+ const: starfive,jh7110-sys-pinctrl
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+
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+ reg:
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+ maxItems: 1
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+
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+ clocks:
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+ maxItems: 1
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+
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+ resets:
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+ maxItems: 1
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+
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+ interrupts:
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+ maxItems: 1
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+
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+ interrupt-controller: true
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+
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+ '#interrupt-cells':
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+ const: 2
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+
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+ gpio-controller: true
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+
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+ '#gpio-cells':
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+ const: 2
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+
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+patternProperties:
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+ '-[0-9]+$':
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+ type: object
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+ additionalProperties: false
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+ patternProperties:
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+ '-pins$':
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+ type: object
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+ description: |
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+ A pinctrl node should contain at least one subnode representing the
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+ pinctrl groups available on the machine. Each subnode will list the
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+ pins it needs, and how they should be configured, with regard to
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+ muxer configuration, bias, input enable/disable, input schmitt
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+ trigger enable/disable, slew-rate and drive strength.
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+ allOf:
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+ - $ref: /schemas/pinctrl/pincfg-node.yaml
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+ - $ref: /schemas/pinctrl/pinmux-node.yaml
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+ additionalProperties: false
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+
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+ properties:
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+ pinmux:
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+ description: |
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+ The list of GPIOs and their mux settings that properties in the
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+ node apply to. This should be set using the GPIOMUX or PINMUX
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+ macros.
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+
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+ bias-disable: true
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+
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+ bias-pull-up:
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+ type: boolean
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+
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+ bias-pull-down:
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+ type: boolean
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+
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+ drive-strength:
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+ enum: [ 2, 4, 8, 12 ]
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+
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+ input-enable: true
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+
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+ input-disable: true
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+
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+ input-schmitt-enable: true
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+
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+ input-schmitt-disable: true
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+
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+ slew-rate:
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+ maximum: 1
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+
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+required:
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+ - compatible
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+ - reg
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+ - clocks
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+ - interrupts
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+ - interrupt-controller
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+ - '#interrupt-cells'
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+ - gpio-controller
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+ - '#gpio-cells'
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ pinctrl@13040000 {
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+ compatible = "starfive,jh7110-sys-pinctrl";
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+ reg = <0x13040000 0x10000>;
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+ clocks = <&syscrg 112>;
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+ resets = <&syscrg 2>;
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+ interrupts = <86>;
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+ interrupt-controller;
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+ #interrupt-cells = <2>;
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+
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+ uart0-0 {
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+ tx-pins {
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+ pinmux = <0xff140005>;
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+ bias-disable;
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+ drive-strength = <12>;
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+ input-disable;
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+ input-schmitt-disable;
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+ slew-rate = <0>;
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+ };
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+
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+ rx-pins {
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+ pinmux = <0x0E000406>;
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+ bias-pull-up;
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+ drive-strength = <2>;
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+ input-enable;
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+ input-schmitt-enable;
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+ slew-rate = <0>;
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+ };
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+ };
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+ };
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+
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+...
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--- a/MAINTAINERS
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+++ b/MAINTAINERS
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@@ -19658,13 +19658,15 @@ F: Documentation/devicetree/bindings/clo
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F: drivers/clk/starfive/clk-starfive-jh71*
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F: include/dt-bindings/clock/starfive?jh71*.h
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-STARFIVE JH7100 PINCTRL DRIVER
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+STARFIVE JH71X0 PINCTRL DRIVERS
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M: Emil Renner Berthing <kernel@esmil.dk>
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+M: Jianlong Huang <jianlong.huang@starfivetech.com>
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L: linux-gpio@vger.kernel.org
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S: Maintained
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-F: Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
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+F: Documentation/devicetree/bindings/pinctrl/starfive,jh71*.yaml
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F: drivers/pinctrl/starfive/
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F: include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h
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+F: include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h
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STARFIVE JH71X0 RESET CONTROLLER DRIVERS
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M: Emil Renner Berthing <kernel@esmil.dk>
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--- /dev/null
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+++ b/include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h
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@@ -0,0 +1,115 @@
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+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
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+/*
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+ * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
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+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
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+ */
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+
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+#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__
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+#define __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__
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+
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+/* sys_iomux pins */
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+#define PAD_GPIO0 0
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+#define PAD_GPIO1 1
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+#define PAD_GPIO2 2
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+#define PAD_GPIO3 3
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+#define PAD_GPIO4 4
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+#define PAD_GPIO5 5
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+#define PAD_GPIO6 6
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+#define PAD_GPIO7 7
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+#define PAD_GPIO8 8
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+#define PAD_GPIO9 9
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+#define PAD_GPIO10 10
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+#define PAD_GPIO11 11
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+#define PAD_GPIO12 12
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+#define PAD_GPIO13 13
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+#define PAD_GPIO14 14
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+#define PAD_GPIO15 15
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+#define PAD_GPIO16 16
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+#define PAD_GPIO17 17
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+#define PAD_GPIO18 18
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+#define PAD_GPIO19 19
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+#define PAD_GPIO20 20
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+#define PAD_GPIO21 21
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+#define PAD_GPIO22 22
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+#define PAD_GPIO23 23
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+#define PAD_GPIO24 24
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+#define PAD_GPIO25 25
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+#define PAD_GPIO26 26
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+#define PAD_GPIO27 27
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+#define PAD_GPIO28 28
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+#define PAD_GPIO29 29
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+#define PAD_GPIO30 30
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+#define PAD_GPIO31 31
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+#define PAD_GPIO32 32
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+#define PAD_GPIO33 33
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+#define PAD_GPIO34 34
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+#define PAD_GPIO35 35
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+#define PAD_GPIO36 36
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+#define PAD_GPIO37 37
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+#define PAD_GPIO38 38
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+#define PAD_GPIO39 39
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+#define PAD_GPIO40 40
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+#define PAD_GPIO41 41
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+#define PAD_GPIO42 42
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+#define PAD_GPIO43 43
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+#define PAD_GPIO44 44
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+#define PAD_GPIO45 45
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+#define PAD_GPIO46 46
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+#define PAD_GPIO47 47
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+#define PAD_GPIO48 48
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+#define PAD_GPIO49 49
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+#define PAD_GPIO50 50
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+#define PAD_GPIO51 51
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+#define PAD_GPIO52 52
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+#define PAD_GPIO53 53
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+#define PAD_GPIO54 54
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+#define PAD_GPIO55 55
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+#define PAD_GPIO56 56
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+#define PAD_GPIO57 57
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+#define PAD_GPIO58 58
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+#define PAD_GPIO59 59
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+#define PAD_GPIO60 60
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+#define PAD_GPIO61 61
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+#define PAD_GPIO62 62
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+#define PAD_GPIO63 63
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+#define PAD_SD0_CLK 64
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+#define PAD_SD0_CMD 65
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+#define PAD_SD0_DATA0 66
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+#define PAD_SD0_DATA1 67
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+#define PAD_SD0_DATA2 68
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+#define PAD_SD0_DATA3 69
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+#define PAD_SD0_DATA4 70
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+#define PAD_SD0_DATA5 71
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+#define PAD_SD0_DATA6 72
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+#define PAD_SD0_DATA7 73
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+#define PAD_SD0_STRB 74
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+#define PAD_GMAC1_MDC 75
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+#define PAD_GMAC1_MDIO 76
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+#define PAD_GMAC1_RXD0 77
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+#define PAD_GMAC1_RXD1 78
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+#define PAD_GMAC1_RXD2 79
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+#define PAD_GMAC1_RXD3 80
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+#define PAD_GMAC1_RXDV 81
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+#define PAD_GMAC1_RXC 82
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+#define PAD_GMAC1_TXD0 83
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+#define PAD_GMAC1_TXD1 84
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+#define PAD_GMAC1_TXD2 85
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+#define PAD_GMAC1_TXD3 86
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+#define PAD_GMAC1_TXEN 87
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+#define PAD_GMAC1_TXC 88
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+#define PAD_QSPI_SCLK 89
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+#define PAD_QSPI_CS0 90
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+#define PAD_QSPI_DATA0 91
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+#define PAD_QSPI_DATA1 92
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+#define PAD_QSPI_DATA2 93
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+#define PAD_QSPI_DATA3 94
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+
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+#define GPOUT_LOW 0
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+#define GPOUT_HIGH 1
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+
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+#define GPOEN_ENABLE 0
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+#define GPOEN_DISABLE 1
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+
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+#define GPI_NONE 255
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+
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+#endif
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