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40379b0ec6
"There are often transient line events when
the system is powered up and initialized and it
is often necessary for the gpio_chip driver to
clear any interrupt flags in hardware before
setting up the gpio chip, especially the
irqchip portions of it."
<http://lists.infradead.org/pipermail/openwrt-devel/2019-June/017630.html>
This patch adds a fix for the APM821XX's interrupt
controller to clear any bogus pending toggled
interrupts that happens on various APM821XX boards
on boot.
The patch also changes the debouce-interval from the
default 5ms debounce interval to 60ms all around.
The default setting caused on occasions that the button
state became stuck in a pressed state, even though the
button was released.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
(backported from commit 971f31bedc)
31 lines
1002 B
Diff
31 lines
1002 B
Diff
From 9b84ad676e248a3e3c81db7f5d39e1739b3780aa Mon Sep 17 00:00:00 2001
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From: Christian Lamparter <chunkeey@gmail.com>
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Date: Sat, 15 Jun 2019 16:35:26 +0200
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Subject: [PATCH] powerpc/4xx/uic: clear pending interrupt after irq type/pol
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change
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When testing out gpio-keys with a button, a spurious
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interrupt (and therefore a key press or release event)
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gets triggered as soon as the driver enables the irq
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line for the first time.
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This patch clears any potential bogus generated interrupt
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that was caused by the switching of the associated irq's
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type and polarity.
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Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
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---
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arch/powerpc/platforms/4xx/uic.c | 1 +
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1 file changed, 1 insertion(+)
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--- a/arch/powerpc/platforms/4xx/uic.c
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+++ b/arch/powerpc/platforms/4xx/uic.c
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@@ -158,6 +158,7 @@ static int uic_set_irq_type(struct irq_d
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mtdcr(uic->dcrbase + UIC_PR, pr);
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mtdcr(uic->dcrbase + UIC_TR, tr);
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+ mtdcr(uic->dcrbase + UIC_SR, ~mask);
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raw_spin_unlock_irqrestore(&uic->lock, flags);
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