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137 lines
3.6 KiB
Diff
137 lines
3.6 KiB
Diff
From 8cf7164b32f2ce228b0c8116fd712484f67c65b5 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
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Date: Wed, 4 Sep 2013 21:28:49 -0300
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Subject: [PATCH] ARM: sun7i: dt: mod0 clocks
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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This commit adds all the mod0 clocks available on A20 to its device
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tree. This list was created by looking at AW's code release.
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Signed-off-by: Emilio López <emilio@elopez.com.ar>
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Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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arch/arm/boot/dts/sun7i-a20.dtsi | 105 +++++++++++++++++++++++++++++++++++++++
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1 file changed, 105 insertions(+)
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diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
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index 0af287e..0596e82 100644
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--- a/arch/arm/boot/dts/sun7i-a20.dtsi
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+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
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@@ -174,6 +174,111 @@
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"apb1_uart2", "apb1_uart3", "apb1_uart4",
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"apb1_uart5", "apb1_uart6", "apb1_uart7";
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};
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+
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+ nand: nand@01c20080 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c20080 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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+
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+ ms: ms@01c20084 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c20084 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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+
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+ mmc0: mmc0@01c20088 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c20088 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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+
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+ mmc1: mmc1@01c2008c {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c2008c 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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+
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+ mmc2: mmc2@01c20090 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c20090 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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+
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+ mmc3: mmc3@01c20094 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c20094 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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+
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+ ts: ts@01c20098 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c20098 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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+
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+ ss: ss@01c2009c {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c2009c 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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+
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+ spi0: spi0@01c200a0 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c200a0 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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+
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+ spi1: spi1@01c200a4 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c200a4 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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+
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+ spi2: spi2@01c200a8 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c200a8 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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+
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+ pata: pata@01c200ac {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c200ac 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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+
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+ ir0: ir0@01c200b0 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c200b0 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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+
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+ ir1: ir1@01c200b4 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c200b4 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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+
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+ spi3: spi3@01c200d4 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c200d4 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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};
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soc@01c00000 {
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--
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1.8.5.1
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