mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-27 09:12:39 +00:00
36746893ac
Fix the issue of dts buswidth cannot be applied properly with spi driver. Fix the name of buswidth to bus-width in dts in order to fit the format in linux spi kernel[1] so that spi-tx-bus-width & spi-rx-bus-width can be parsed properly. [1] Documentation/devicetree/bindings/spi/spi-controller.yaml Signed-off-by: Chen Minqiang <ptpt52@gmail.com>
158 lines
3.7 KiB
Diff
158 lines
3.7 KiB
Diff
From f4029538f063a845dc9aae46cce4cf386e6253a5 Mon Sep 17 00:00:00 2001
|
|
From: Sam Shih <sam.shih@mediatek.com>
|
|
Date: Fri, 18 Nov 2022 20:01:21 +0100
|
|
Subject: [PATCH 06/19] arm64: dts: mt7986: add spi related device nodes
|
|
|
|
This patch adds spi support for MT7986.
|
|
|
|
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
|
|
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
|
|
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
|
Link: https://lore.kernel.org/r/20221118190126.100895-7-linux@fw-web.de
|
|
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
|
|
---
|
|
arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 35 ++++++++++++++++++++
|
|
arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 28 ++++++++++++++++
|
|
arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 35 ++++++++++++++++++++
|
|
3 files changed, 98 insertions(+)
|
|
|
|
--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
|
|
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
|
|
@@ -59,6 +59,20 @@
|
|
};
|
|
|
|
&pio {
|
|
+ spi_flash_pins: spi-flash-pins {
|
|
+ mux {
|
|
+ function = "spi";
|
|
+ groups = "spi0", "spi0_wp_hold";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spic_pins: spic-pins {
|
|
+ mux {
|
|
+ function = "spi";
|
|
+ groups = "spi1_2";
|
|
+ };
|
|
+ };
|
|
+
|
|
uart1_pins: uart1-pins {
|
|
mux {
|
|
function = "uart";
|
|
@@ -105,6 +119,27 @@
|
|
};
|
|
};
|
|
|
|
+&spi0 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&spi_flash_pins>;
|
|
+ cs-gpios = <0>, <0>;
|
|
+ status = "okay";
|
|
+ spi_nand: spi_nand@0 {
|
|
+ compatible = "spi-nand";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <10000000>;
|
|
+ spi-tx-bus-width = <4>;
|
|
+ spi-rx-bus-width = <4>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&spi1 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&spic_pins>;
|
|
+ cs-gpios = <0>, <0>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
&switch {
|
|
ports {
|
|
#address-cells = <1>;
|
|
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
|
|
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
|
|
@@ -294,6 +294,34 @@
|
|
status = "disabled";
|
|
};
|
|
|
|
+ spi0: spi@1100a000 {
|
|
+ compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ reg = <0 0x1100a000 0 0x100>;
|
|
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&topckgen CLK_TOP_MPLL_D2>,
|
|
+ <&topckgen CLK_TOP_SPI_SEL>,
|
|
+ <&infracfg CLK_INFRA_SPI0_CK>,
|
|
+ <&infracfg CLK_INFRA_SPI0_HCK_CK>;
|
|
+ clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ spi1: spi@1100b000 {
|
|
+ compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ reg = <0 0x1100b000 0 0x100>;
|
|
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&topckgen CLK_TOP_MPLL_D2>,
|
|
+ <&topckgen CLK_TOP_SPIM_MST_SEL>,
|
|
+ <&infracfg CLK_INFRA_SPI1_CK>,
|
|
+ <&infracfg CLK_INFRA_SPI1_HCK_CK>;
|
|
+ clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
ethsys: syscon@15000000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
|
|
+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
|
|
@@ -100,6 +100,20 @@
|
|
};
|
|
|
|
&pio {
|
|
+ spi_flash_pins: spi-flash-pins {
|
|
+ mux {
|
|
+ function = "spi";
|
|
+ groups = "spi0", "spi0_wp_hold";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spic_pins: spic-pins {
|
|
+ mux {
|
|
+ function = "spi";
|
|
+ groups = "spi1_2";
|
|
+ };
|
|
+ };
|
|
+
|
|
wf_2g_5g_pins: wf-2g-5g-pins {
|
|
mux {
|
|
function = "wifi";
|
|
@@ -132,6 +146,27 @@
|
|
};
|
|
};
|
|
|
|
+&spi0 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&spi_flash_pins>;
|
|
+ cs-gpios = <0>, <0>;
|
|
+ status = "okay";
|
|
+ spi_nand: spi_nand@0 {
|
|
+ compatible = "spi-nand";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <10000000>;
|
|
+ spi-tx-bus-width = <4>;
|
|
+ spi-rx-bus-width = <4>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&spi1 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&spic_pins>;
|
|
+ cs-gpios = <0>, <0>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
&uart0 {
|
|
status = "okay";
|
|
};
|