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572ea68070
Import pending patches adding support for MT7988 and provide builds for the reference board for all possible boot media. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
607 lines
16 KiB
Diff
607 lines
16 KiB
Diff
From 884430dadcc2c5d0a2b248795001955a9fa5a1a9 Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Wed, 19 Jul 2023 17:17:49 +0800
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Subject: [PATCH 28/29] arm: mediatek: add support for MediaTek MT7988 SoC
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This patch adds basic support for MediaTek MT7988 SoC.
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This includes files that will initialize the SoC after boot and
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its device tree.
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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arch/arm/dts/mt7988-u-boot.dtsi | 25 ++
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arch/arm/dts/mt7988.dtsi | 391 ++++++++++++++++++
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arch/arm/mach-mediatek/Kconfig | 13 +-
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arch/arm/mach-mediatek/Makefile | 1 +
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arch/arm/mach-mediatek/mt7988/Makefile | 4 +
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arch/arm/mach-mediatek/mt7988/init.c | 63 +++
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arch/arm/mach-mediatek/mt7988/lowlevel_init.S | 30 ++
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7 files changed, 526 insertions(+), 1 deletion(-)
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create mode 100644 arch/arm/dts/mt7988-u-boot.dtsi
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create mode 100644 arch/arm/dts/mt7988.dtsi
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create mode 100644 arch/arm/mach-mediatek/mt7988/Makefile
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create mode 100644 arch/arm/mach-mediatek/mt7988/init.c
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create mode 100644 arch/arm/mach-mediatek/mt7988/lowlevel_init.S
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--- /dev/null
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+++ b/arch/arm/dts/mt7988-u-boot.dtsi
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@@ -0,0 +1,25 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Copyright (c) 2022 MediaTek Inc.
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+ * Author: Sam Shih <sam.shih@mediatek.com>
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+ */
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+
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+&system_clk {
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+ bootph-all;
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+};
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+
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+&spi_clk {
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+ bootph-all;
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+};
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+
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+&uart0 {
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+ bootph-all;
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+};
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+
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+&uart1 {
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+ bootph-all;
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+};
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+
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+&uart2 {
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+ bootph-all;
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+};
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--- /dev/null
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+++ b/arch/arm/dts/mt7988.dtsi
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@@ -0,0 +1,391 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Copyright (c) 2022 MediaTek Inc.
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+ * Author: Sam Shih <sam.shih@mediatek.com>
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+ */
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+
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+#include <dt-bindings/interrupt-controller/irq.h>
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+#include <dt-bindings/interrupt-controller/arm-gic.h>
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+#include <dt-bindings/clock/mt7988-clk.h>
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+#include <dt-bindings/reset/mt7988-reset.h>
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+#include <dt-bindings/gpio/gpio.h>
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+
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+/ {
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+ compatible = "mediatek,mt7988-rfb";
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+ interrupt-parent = <&gic>;
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+
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+ cpus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ cpu0: cpu@0 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a73";
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+ reg = <0x0>;
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+ mediatek,hwver = <&hwver>;
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+ };
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+
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+ cpu1: cpu@1 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a73";
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+ reg = <0x1>;
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+ mediatek,hwver = <&hwver>;
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+ };
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+
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+ cpu2: cpu@2 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a73";
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+ reg = <0x2>;
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+ mediatek,hwver = <&hwver>;
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+ };
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+
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+ cpu3: cpu@3 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a73";
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+ reg = <0x3>;
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+ mediatek,hwver = <&hwver>;
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+ };
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+ };
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+
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+ system_clk: dummy40m {
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+ compatible = "fixed-clock";
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+ clock-frequency = <40000000>;
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+ #clock-cells = <0>;
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+ };
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+
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+ spi_clk: dummy208m {
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+ compatible = "fixed-clock";
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+ clock-frequency = <208000000>;
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+ #clock-cells = <0>;
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+ };
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+
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+ hwver: hwver {
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+ compatible = "mediatek,hwver", "syscon";
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+ reg = <0 0x8000000 0 0x1000>;
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+ };
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+
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+ timer {
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+ compatible = "arm,armv8-timer";
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+ interrupt-parent = <&gic>;
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+ clock-frequency = <13000000>;
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+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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+ };
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+
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+ watchdog: watchdog@1001c000 {
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+ compatible = "mediatek,mt7622-wdt",
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+ "mediatek,mt6589-wdt",
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+ "syscon";
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+ reg = <0 0x1001c000 0 0x1000>;
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+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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+ #reset-cells = <1>;
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+ };
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+
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+ gic: interrupt-controller@c000000 {
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+ compatible = "arm,gic-v3";
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+ #interrupt-cells = <3>;
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+ interrupt-parent = <&gic>;
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+ interrupt-controller;
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+ reg = <0 0x0c000000 0 0x40000>, /* GICD */
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+ <0 0x0c080000 0 0x200000>; /* GICR */
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+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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+ };
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+
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+ infracfg_ao_cgs: infracfg_ao_cgs@10001000 {
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+ compatible = "mediatek,mt7988-infracfg_ao_cgs", "syscon";
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+ reg = <0 0x10001000 0 0x1000>;
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+ clock-parent = <&infracfg_ao>;
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+ #clock-cells = <1>;
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+ };
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+
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+ apmixedsys: apmixedsys@1001e000 {
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+ compatible = "mediatek,mt7988-fixed-plls", "syscon";
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+ reg = <0 0x1001e000 0 0x1000>;
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+ #clock-cells = <1>;
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+ };
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+
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+ topckgen: topckgen@1001b000 {
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+ compatible = "mediatek,mt7988-topckgen", "syscon";
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+ reg = <0 0x1001b000 0 0x1000>;
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+ clock-parent = <&apmixedsys>;
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+ #clock-cells = <1>;
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+ };
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+
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+ pinctrl: pinctrl@1001f000 {
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+ compatible = "mediatek,mt7988-pinctrl";
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+ reg = <0 0x1001f000 0 0x1000>,
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+ <0 0x11c10000 0 0x1000>,
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+ <0 0x11d00000 0 0x1000>,
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+ <0 0x11d20000 0 0x1000>,
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+ <0 0x11e00000 0 0x1000>,
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+ <0 0x11f00000 0 0x1000>,
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+ <0 0x1000b000 0 0x1000>;
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+ reg-names = "gpio_base", "iocfg_tr_base", "iocfg_br_base",
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+ "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base",
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+ "eint";
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+ gpio: gpio-controller {
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ };
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+ };
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+
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+ sgmiisys0: syscon@10060000 {
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+ compatible = "mediatek,mt7988-sgmiisys_0", "syscon";
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+ reg = <0 0x10060000 0 0x1000>;
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+ clock-parent = <&topckgen>;
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+ #clock-cells = <1>;
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+ };
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+
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+ sgmiisys1: syscon@10070000 {
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+ compatible = "mediatek,mt7988-sgmiisys_1", "syscon";
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+ reg = <0 0x10070000 0 0x1000>;
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+ clock-parent = <&topckgen>;
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+ #clock-cells = <1>;
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+ };
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+
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+ usxgmiisys0: syscon@10080000 {
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+ compatible = "mediatek,mt7988-usxgmiisys_0", "syscon";
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+ reg = <0 0x10080000 0 0x1000>;
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+ clock-parent = <&topckgen>;
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+ #clock-cells = <1>;
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+ };
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+
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+ usxgmiisys1: syscon@10081000 {
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+ compatible = "mediatek,mt7988-usxgmiisys_1", "syscon";
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+ reg = <0 0x10081000 0 0x1000>;
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+ clock-parent = <&topckgen>;
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+ #clock-cells = <1>;
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+ };
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+
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+ xfi_pextp0: syscon@11f20000 {
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+ compatible = "mediatek,mt7988-xfi_pextp_0", "syscon";
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+ reg = <0 0x11f20000 0 0x10000>;
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+ clock-parent = <&topckgen>;
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+ #clock-cells = <1>;
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+ };
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+
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+ xfi_pextp1: syscon@11f30000 {
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+ compatible = "mediatek,mt7988-xfi_pextp_1", "syscon";
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+ reg = <0 0x11f30000 0 0x10000>;
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+ clock-parent = <&topckgen>;
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+ #clock-cells = <1>;
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+ };
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+
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+ xfi_pll: syscon@11f40000 {
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+ compatible = "mediatek,mt7988-xfi_pll", "syscon";
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+ reg = <0 0x11f40000 0 0x1000>;
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+ clock-parent = <&topckgen>;
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+ #clock-cells = <1>;
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+ };
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+
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+ topmisc: topmisc@11d10000 {
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+ compatible = "mediatek,mt7988-topmisc", "syscon",
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+ "mediatek,mt7988-power-controller";
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+ reg = <0 0x11d10000 0 0x10000>;
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+ clock-parent = <&topckgen>;
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+ #clock-cells = <1>;
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+ };
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+
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+ infracfg_ao: infracfg@10001000 {
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+ compatible = "mediatek,mt7988-infracfg", "syscon";
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+ reg = <0 0x10001000 0 0x1000>;
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+ clock-parent = <&topckgen>;
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+ #clock-cells = <1>;
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+ };
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+
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+ uart0: serial@11000000 {
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+ compatible = "mediatek,hsuart";
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+ reg = <0 0x11000000 0 0x100>;
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+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART0_CK>;
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+ assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
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+ <&infracfg_ao CK_INFRA_MUX_UART0_SEL>;
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+ assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
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+ <&infracfg_ao CK_INFRA_UART_O0>;
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+ status = "disabled";
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+ };
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+
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+ uart1: serial@11000100 {
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+ compatible = "mediatek,hsuart";
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+ reg = <0 0x11000100 0 0x100>;
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+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART1_CK>;
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+ assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
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+ <&infracfg_ao CK_INFRA_MUX_UART1_SEL>;
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+ assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
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+ <&infracfg_ao CK_INFRA_UART_O1>;
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+ status = "disabled";
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+ };
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+
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+ uart2: serial@11000200 {
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+ compatible = "mediatek,hsuart";
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+ reg = <0 0x11000200 0 0x100>;
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+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART2_CK>;
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+ assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
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+ <&infracfg_ao CK_INFRA_MUX_UART2_SEL>;
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+ assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
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+ <&infracfg_ao CK_INFRA_UART_O2>;
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+ status = "disabled";
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+ };
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+
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+ i2c0: i2c@11003000 {
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+ compatible = "mediatek,mt7988-i2c",
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+ "mediatek,mt7981-i2c";
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+ reg = <0 0x11003000 0 0x1000>,
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+ <0 0x10217080 0 0x80>;
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+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
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+ clock-div = <1>;
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+ clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
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+ <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
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+ clock-names = "main", "dma";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ i2c1: i2c@11004000 {
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+ compatible = "mediatek,mt7988-i2c",
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+ "mediatek,mt7981-i2c";
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+ reg = <0 0x11004000 0 0x1000>,
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+ <0 0x10217100 0 0x80>;
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+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
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+ clock-div = <1>;
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+ clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
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+ <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
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+ clock-names = "main", "dma";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ i2c2: i2c@11005000 {
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+ compatible = "mediatek,mt7988-i2c",
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+ "mediatek,mt7981-i2c";
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+ reg = <0 0x11005000 0 0x1000>,
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+ <0 0x10217180 0 0x80>;
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+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
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+ clock-div = <1>;
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+ clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
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+ <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
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+ clock-names = "main", "dma";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ pwm: pwm@10048000 {
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+ compatible = "mediatek,mt7988-pwm";
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+ reg = <0 0x10048000 0 0x1000>;
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+ #pwm-cells = <2>;
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+ clocks = <&infracfg_ao CK_INFRA_66M_PWM_BCK>,
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+ <&infracfg_ao CK_INFRA_66M_PWM_HCK>,
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+ <&infracfg_ao CK_INFRA_66M_PWM_CK1>,
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+ <&infracfg_ao CK_INFRA_66M_PWM_CK2>,
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+ <&infracfg_ao CK_INFRA_66M_PWM_CK3>,
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+ <&infracfg_ao CK_INFRA_66M_PWM_CK4>,
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+ <&infracfg_ao CK_INFRA_66M_PWM_CK5>,
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+ <&infracfg_ao CK_INFRA_66M_PWM_CK6>,
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+ <&infracfg_ao CK_INFRA_66M_PWM_CK7>,
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+ <&infracfg_ao CK_INFRA_66M_PWM_CK8>;
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+ clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
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+ "pwm4","pwm5","pwm6","pwm7","pwm8";
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+ status = "disabled";
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+ };
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+
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+ snand: snand@11001000 {
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+ compatible = "mediatek,mt7988-snand",
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+ "mediatek,mt7986-snand";
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+ reg = <0 0x11001000 0 0x1000>,
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+ <0 0x11002000 0 0x1000>;
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+ reg-names = "nfi", "ecc";
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+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&infracfg_ao CK_INFRA_SPINFI>,
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+ <&infracfg_ao CK_INFRA_NFI>,
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+ <&infracfg_ao CK_INFRA_66M_NFI_HCK>;
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+ clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
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+ assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
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+ <&topckgen CK_TOP_NFI1X_SEL>;
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+ assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>,
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+ <&topckgen CK_TOP_CB_M_D8>;
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+ status = "disabled";
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+ };
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+
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+ spi0: spi@1100a000 {
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+ compatible = "mediatek,ipm-spi";
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+ reg = <0 0x11007000 0 0x100>;
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+ clocks = <&spi_clk>,
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+ <&spi_clk>;
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+ clock-names = "sel-clk", "spi-clk";
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+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ };
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+
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+ spi1: spi@1100b000 {
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+ compatible = "mediatek,ipm-spi";
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+ reg = <0 0x11008000 0 0x100>;
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+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ };
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+
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+ spi2: spi@11009000 {
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+ compatible = "mediatek,ipm-spi";
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+ reg = <0 0x11009000 0 0x100>;
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+ clocks = <&spi_clk>,
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+ <&spi_clk>;
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+ clock-names = "sel-clk", "spi-clk";
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+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ };
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+
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+ mmc0: mmc@11230000 {
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+ compatible = "mediatek,mt7988-mmc",
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+ "mediatek,mt7986-mmc";
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+ reg = <0 0x11230000 0 0x1000>;
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+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&infracfg_ao_cgs CK_INFRA_MSDC400>,
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+ <&infracfg_ao_cgs CK_INFRA_MSDC2_HCK>,
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+ <&infracfg_ao_cgs CK_INFRA_133M_MSDC_0_HCK>,
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+ <&infracfg_ao_cgs CK_INFRA_66M_MSDC_0_HCK>;
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+ clock-names = "source", "hclk", "source_cg", "axi_cg";
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+ status = "disabled";
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+ };
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+
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+ ethdma: syscon@15000000 {
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+ compatible = "mediatek,mt7988-ethdma", "syscon";
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+ reg = <0 0x15000000 0 0x20000>;
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+ clock-parent = <&topckgen>;
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
|
|
+ };
|
|
+
|
|
+ ethwarp: syscon@15031000 {
|
|
+ compatible = "mediatek,mt7988-ethwarp", "syscon";
|
|
+ reg = <0 0x15031000 0 0x1000>;
|
|
+ clock-parent = <&topckgen>;
|
|
+ #clock-cells = <1>;
|
|
+ #reset-cells = <1>;
|
|
+ };
|
|
+
|
|
+ eth: ethernet@15100000 {
|
|
+ compatible = "mediatek,mt7988-eth", "syscon";
|
|
+ reg = <0 0x15100000 0 0x20000>;
|
|
+ mediatek,ethsys = <ðdma>;
|
|
+ mediatek,sgmiisys = <&sgmiisys0>;
|
|
+ mediatek,usxgmiisys = <&usxgmiisys0>;
|
|
+ mediatek,xfi_pextp = <&xfi_pextp0>;
|
|
+ mediatek,xfi_pll = <&xfi_pll>;
|
|
+ mediatek,infracfg = <&topmisc>;
|
|
+ mediatek,toprgu = <&watchdog>;
|
|
+ resets = <ðdma ETHDMA_FE_RST>, <ðwarp ETHWARP_GSW_RST>;
|
|
+ reset-names = "fe", "mcm";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ mediatek,mcm;
|
|
+ status = "disabled";
|
|
+ };
|
|
+};
|
|
--- a/arch/arm/mach-mediatek/Kconfig
|
|
+++ b/arch/arm/mach-mediatek/Kconfig
|
|
@@ -58,6 +58,15 @@ config TARGET_MT7986
|
|
including UART, SPI, SPI flash, USB3.0, MMC, NAND, SNFI, PWM, PCIe,
|
|
Gigabit Ethernet, I2C, built-in 4x4 Wi-Fi, and PCIe.
|
|
|
|
+config TARGET_MT7988
|
|
+ bool "MediaTek MT7988 SoC"
|
|
+ select ARM64
|
|
+ select CPU
|
|
+ help
|
|
+ The MediaTek MT7988 is a ARM64-based SoC with a quad-core Cortex-A73.
|
|
+ including UART, SPI, SPI flash, USB3.0, MMC, NAND, SNFI, PWM, PCIe,
|
|
+ 10 Gigabit Ethernet , I2C, and PCIe.
|
|
+
|
|
config TARGET_MT8183
|
|
bool "MediaTek MT8183 SoC"
|
|
select ARM64
|
|
@@ -104,6 +113,7 @@ config SYS_BOARD
|
|
default "mt7629" if TARGET_MT7629
|
|
default "mt7981" if TARGET_MT7981
|
|
default "mt7986" if TARGET_MT7986
|
|
+ default "mt7988" if TARGET_MT7988
|
|
default "mt8183" if TARGET_MT8183
|
|
default "mt8512" if TARGET_MT8512
|
|
default "mt8516" if TARGET_MT8516
|
|
@@ -121,6 +131,7 @@ config SYS_CONFIG_NAME
|
|
default "mt7629" if TARGET_MT7629
|
|
default "mt7981" if TARGET_MT7981
|
|
default "mt7986" if TARGET_MT7986
|
|
+ default "mt7988" if TARGET_MT7988
|
|
default "mt8183" if TARGET_MT8183
|
|
default "mt8512" if TARGET_MT8512
|
|
default "mt8516" if TARGET_MT8516
|
|
@@ -135,7 +146,7 @@ config MTK_BROM_HEADER_INFO
|
|
string
|
|
default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7622
|
|
default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
|
|
- default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986
|
|
+ default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 || TARGET_MT7988
|
|
default "lk=1" if TARGET_MT7623
|
|
|
|
source "board/mediatek/mt7629/Kconfig"
|
|
--- a/arch/arm/mach-mediatek/Makefile
|
|
+++ b/arch/arm/mach-mediatek/Makefile
|
|
@@ -9,6 +9,7 @@ obj-$(CONFIG_TARGET_MT7623) += mt7623/
|
|
obj-$(CONFIG_TARGET_MT7629) += mt7629/
|
|
obj-$(CONFIG_TARGET_MT7981) += mt7981/
|
|
obj-$(CONFIG_TARGET_MT7986) += mt7986/
|
|
+obj-$(CONFIG_TARGET_MT7988) += mt7988/
|
|
obj-$(CONFIG_TARGET_MT8183) += mt8183/
|
|
obj-$(CONFIG_TARGET_MT8516) += mt8516/
|
|
obj-$(CONFIG_TARGET_MT8518) += mt8518/
|
|
--- /dev/null
|
|
+++ b/arch/arm/mach-mediatek/mt7988/Makefile
|
|
@@ -0,0 +1,4 @@
|
|
+# SPDX-License-Identifier: GPL-2.0
|
|
+
|
|
+obj-y += init.o
|
|
+obj-y += lowlevel_init.o
|
|
--- /dev/null
|
|
+++ b/arch/arm/mach-mediatek/mt7988/init.c
|
|
@@ -0,0 +1,63 @@
|
|
+// SPDX-License-Identifier: GPL-2.0
|
|
+/*
|
|
+ * Copyright (C) 2022 MediaTek Inc.
|
|
+ * Author: Sam Shih <sam.shih@mediatek.com>
|
|
+ */
|
|
+
|
|
+#include <fdtdec.h>
|
|
+#include <init.h>
|
|
+#include <asm/armv8/mmu.h>
|
|
+#include <asm/global_data.h>
|
|
+#include <asm/u-boot.h>
|
|
+#include <asm/system.h>
|
|
+
|
|
+DECLARE_GLOBAL_DATA_PTR;
|
|
+
|
|
+#define SZ_8G _AC(0x200000000, ULL)
|
|
+
|
|
+int dram_init(void)
|
|
+{
|
|
+ int ret;
|
|
+
|
|
+ ret = fdtdec_setup_mem_size_base();
|
|
+ if (ret)
|
|
+ return ret;
|
|
+
|
|
+ gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_8G);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+int dram_init_banksize(void)
|
|
+{
|
|
+ gd->bd->bi_dram[0].start = gd->ram_base;
|
|
+ gd->bd->bi_dram[0].size = gd->ram_size;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+void reset_cpu(ulong addr)
|
|
+{
|
|
+ psci_system_reset();
|
|
+}
|
|
+
|
|
+static struct mm_region mt7988_mem_map[] = {
|
|
+ {
|
|
+ /* DDR */
|
|
+ .virt = 0x40000000UL,
|
|
+ .phys = 0x40000000UL,
|
|
+ .size = 0x200000000ULL,
|
|
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
|
|
+ }, {
|
|
+ .virt = 0x00000000UL,
|
|
+ .phys = 0x00000000UL,
|
|
+ .size = 0x40000000UL,
|
|
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
|
+ PTE_BLOCK_NON_SHARE |
|
|
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
|
+ }, {
|
|
+ 0,
|
|
+ }
|
|
+};
|
|
+
|
|
+struct mm_region *mem_map = mt7988_mem_map;
|
|
--- /dev/null
|
|
+++ b/arch/arm/mach-mediatek/mt7988/lowlevel_init.S
|
|
@@ -0,0 +1,30 @@
|
|
+/* SPDX-License-Identifier: GPL-2.0 */
|
|
+/*
|
|
+ * Copyright (C) 2020 MediaTek Inc.
|
|
+ * Author: Sam Shih <sam.shih@mediatek.com>
|
|
+ */
|
|
+
|
|
+/*
|
|
+ * Switch from AArch64 EL2 to AArch32 EL2
|
|
+ * @param inputs:
|
|
+ * x0: argument, zero
|
|
+ * x1: machine nr
|
|
+ * x2: fdt address
|
|
+ * x3: input argument
|
|
+ * x4: kernel entry point
|
|
+ * @param outputs for secure firmware:
|
|
+ * x0: function id
|
|
+ * x1: kernel entry point
|
|
+ * x2: machine nr
|
|
+ * x3: fdt address
|
|
+*/
|
|
+
|
|
+.global armv8_el2_to_aarch32
|
|
+armv8_el2_to_aarch32:
|
|
+ mov x3, x2
|
|
+ mov x2, x1
|
|
+ mov x1, x4
|
|
+ mov x4, #0
|
|
+ ldr x0, =0x82000200
|
|
+ SMC #0
|
|
+ ret
|