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77e97abf12
Also removes random module and switches to new bcm2711 thermal driver. Boot tested on RPi 4B v1.1 4G. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
87 lines
2.9 KiB
Diff
87 lines
2.9 KiB
Diff
From a294de7c4782f91fe724e4e5b05fd99798d50760 Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime@cerno.tech>
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Date: Mon, 13 Jan 2020 13:39:20 +0100
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Subject: [PATCH] drm/vc4: crtc: Add FIFO depth to vc4_crtc_data
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Not all pixelvalve FIFOs in vc5 have the same depth, so we need to add that
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to our vc4_crtc_data structure to be able to compute the fill level
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properly later on.
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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---
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drivers/gpu/drm/vc4/vc4_crtc.c | 20 ++++++++++++++++----
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drivers/gpu/drm/vc4/vc4_drv.h | 3 +++
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2 files changed, 19 insertions(+), 4 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_crtc.c
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+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
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@@ -250,11 +250,20 @@ vc4_crtc_update_gamma_lut(struct drm_crt
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vc4_crtc_lut_load(crtc);
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}
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-
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-static u32 vc4_get_fifo_full_level(u32 format)
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+static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format)
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{
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- static const u32 fifo_len_bytes = 64;
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+ u32 fifo_len_bytes = vc4_crtc->data->fifo_depth;
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+ /*
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+ * Pixels are pulled from the HVS if the number of bytes is
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+ * lower than the FIFO full level.
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+ *
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+ * The latency of the pixel fetch mechanism is 6 pixels, so we
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+ * need to convert those 6 pixels in bytes, depending on the
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+ * format, and then substract that from the length of the FIFO
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+ * to make sure we never end up in a situation where the FIFO
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+ * is full.
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+ */
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switch (format) {
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case PV_CONTROL_FORMAT_DSIV_16:
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case PV_CONTROL_FORMAT_DSIC_16:
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@@ -369,7 +378,7 @@ static void vc4_crtc_config_pv(struct dr
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CRTC_WRITE(PV_CONTROL,
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VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
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- VC4_SET_FIELD(vc4_get_fifo_full_level(format),
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+ VC4_SET_FIELD(vc4_get_fifo_full_level(vc4_crtc, format),
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PV_CONTROL_FIFO_LEVEL) |
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VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
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PV_CONTROL_CLR_AT_START |
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@@ -1067,6 +1076,7 @@ static const struct vc4_crtc_data bcm283
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.hvs_available_channels = BIT(0),
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.hvs_output = 0,
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.debugfs_name = "crtc0_regs",
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+ .fifo_depth = 64,
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.pixels_per_clock = 1,
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.encoder_types = {
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[PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
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@@ -1078,6 +1088,7 @@ static const struct vc4_crtc_data bcm283
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.hvs_available_channels = BIT(2),
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.hvs_output = 2,
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.debugfs_name = "crtc1_regs",
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+ .fifo_depth = 64,
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.pixels_per_clock = 1,
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.encoder_types = {
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[PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
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@@ -1089,6 +1100,7 @@ static const struct vc4_crtc_data bcm283
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.hvs_available_channels = BIT(1),
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.hvs_output = 1,
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.debugfs_name = "crtc2_regs",
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+ .fifo_depth = 64,
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.pixels_per_clock = 1,
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.encoder_types = {
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[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
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--- a/drivers/gpu/drm/vc4/vc4_drv.h
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+++ b/drivers/gpu/drm/vc4/vc4_drv.h
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@@ -452,6 +452,9 @@ to_vc4_encoder(struct drm_encoder *encod
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}
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struct vc4_crtc_data {
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+ /* Depth of the PixelValve FIFO in bytes */
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+ unsigned int fifo_depth;
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+
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/* Which channels of the HVS can the output source from */
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unsigned int hvs_available_channels;
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