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3f41360eb7
Currently we fix interrupts/timers for the secondary CPU by patching vsmp_init_secondary(). Get a little bit more generic and use the upstream recommended way instead. Additionally avoid a check around register_cps_smp_ops() because it does that itself. See https://lkml.org/lkml/2022/9/12/522 Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
34 lines
913 B
Diff
34 lines
913 B
Diff
--- a/arch/mips/kernel/Makefile
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+++ b/arch/mips/kernel/Makefile
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@@ -27,6 +27,7 @@ obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm14
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obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o
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obj-$(CONFIG_CEVT_DS1287) += cevt-ds1287.o
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obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o
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+obj-$(CONFIG_CEVT_RTL9300) += cevt-rtl9300.o
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obj-$(CONFIG_CEVT_SB1250) += cevt-sb1250.o
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obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o
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obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o
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--- a/arch/mips/include/asm/time.h
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+++ b/arch/mips/include/asm/time.h
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@@ -15,6 +15,8 @@
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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+extern void rtl9300_clockevent_init(void);
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+
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extern spinlock_t rtc_lock;
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/*
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@@ -43,6 +45,11 @@ extern int r4k_clockevent_init(void);
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static inline int mips_clockevent_init(void)
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{
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+#ifdef CONFIG_CEVT_RTL9300
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+ rtl9300_clockevent_init();
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+ return 0;
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+#endif
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+
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#ifdef CONFIG_CEVT_R4K
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return r4k_clockevent_init();
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#else
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