mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-30 18:47:06 +00:00
3ecfc24c51
Sync patch with upstream version and tag them.
Minor changes done to Pinctrl patch to support older kernel.
Patch automatically refreshed with make target/linux/refresh.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
(cherry picked from commit a5d23e3aee)
153 lines
3.9 KiB
Diff
153 lines
3.9 KiB
Diff
From f98eded9e9ab048c88ff59c5523e703a6ced5523 Mon Sep 17 00:00:00 2001
|
|
From: Lorenzo Bianconi <lorenzo@kernel.org>
|
|
Date: Tue, 12 Nov 2024 01:08:52 +0100
|
|
Subject: [PATCH 4/6] clk: en7523: fix estimation of fixed rate for EN7581
|
|
|
|
Introduce en7581_base_clks array in order to define per-SoC fixed-rate
|
|
clock parameters and fix wrong parameters for emi, npu and crypto EN7581
|
|
clocks
|
|
|
|
Fixes: 66bc47326ce2 ("clk: en7523: Add EN7581 support")
|
|
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
|
|
Link: https://lore.kernel.org/r/20241112-clk-en7581-syscon-v2-5-8ada5e394ae4@kernel.org
|
|
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
---
|
|
drivers/clk/clk-en7523.c | 105 ++++++++++++++++++++++++++++++++++++++-
|
|
1 file changed, 103 insertions(+), 2 deletions(-)
|
|
|
|
--- a/drivers/clk/clk-en7523.c
|
|
+++ b/drivers/clk/clk-en7523.c
|
|
@@ -37,6 +37,7 @@
|
|
#define REG_NP_SCU_SSTR 0x9c
|
|
#define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13)
|
|
#define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11)
|
|
+#define REG_CRYPTO_CLKSRC2 0x20c
|
|
|
|
#define REG_RST_CTRL2 0x00
|
|
#define REG_RST_CTRL1 0x04
|
|
@@ -89,6 +90,10 @@ static const u32 emi_base[] = { 33300000
|
|
static const u32 bus_base[] = { 500000000, 540000000 };
|
|
static const u32 slic_base[] = { 100000000, 3125000 };
|
|
static const u32 npu_base[] = { 333000000, 400000000, 500000000 };
|
|
+/* EN7581 */
|
|
+static const u32 emi7581_base[] = { 540000000, 480000000, 400000000, 300000000 };
|
|
+static const u32 npu7581_base[] = { 800000000, 750000000, 720000000, 600000000 };
|
|
+static const u32 crypto_base[] = { 540000000, 480000000 };
|
|
|
|
static const struct en_clk_desc en7523_base_clks[] = {
|
|
{
|
|
@@ -186,6 +191,102 @@ static const struct en_clk_desc en7523_b
|
|
}
|
|
};
|
|
|
|
+static const struct en_clk_desc en7581_base_clks[] = {
|
|
+ {
|
|
+ .id = EN7523_CLK_GSW,
|
|
+ .name = "gsw",
|
|
+
|
|
+ .base_reg = REG_GSW_CLK_DIV_SEL,
|
|
+ .base_bits = 1,
|
|
+ .base_shift = 8,
|
|
+ .base_values = gsw_base,
|
|
+ .n_base_values = ARRAY_SIZE(gsw_base),
|
|
+
|
|
+ .div_bits = 3,
|
|
+ .div_shift = 0,
|
|
+ .div_step = 1,
|
|
+ .div_offset = 1,
|
|
+ }, {
|
|
+ .id = EN7523_CLK_EMI,
|
|
+ .name = "emi",
|
|
+
|
|
+ .base_reg = REG_EMI_CLK_DIV_SEL,
|
|
+ .base_bits = 2,
|
|
+ .base_shift = 8,
|
|
+ .base_values = emi7581_base,
|
|
+ .n_base_values = ARRAY_SIZE(emi7581_base),
|
|
+
|
|
+ .div_bits = 3,
|
|
+ .div_shift = 0,
|
|
+ .div_step = 1,
|
|
+ .div_offset = 1,
|
|
+ }, {
|
|
+ .id = EN7523_CLK_BUS,
|
|
+ .name = "bus",
|
|
+
|
|
+ .base_reg = REG_BUS_CLK_DIV_SEL,
|
|
+ .base_bits = 1,
|
|
+ .base_shift = 8,
|
|
+ .base_values = bus_base,
|
|
+ .n_base_values = ARRAY_SIZE(bus_base),
|
|
+
|
|
+ .div_bits = 3,
|
|
+ .div_shift = 0,
|
|
+ .div_step = 1,
|
|
+ .div_offset = 1,
|
|
+ }, {
|
|
+ .id = EN7523_CLK_SLIC,
|
|
+ .name = "slic",
|
|
+
|
|
+ .base_reg = REG_SPI_CLK_FREQ_SEL,
|
|
+ .base_bits = 1,
|
|
+ .base_shift = 0,
|
|
+ .base_values = slic_base,
|
|
+ .n_base_values = ARRAY_SIZE(slic_base),
|
|
+
|
|
+ .div_reg = REG_SPI_CLK_DIV_SEL,
|
|
+ .div_bits = 5,
|
|
+ .div_shift = 24,
|
|
+ .div_val0 = 20,
|
|
+ .div_step = 2,
|
|
+ }, {
|
|
+ .id = EN7523_CLK_SPI,
|
|
+ .name = "spi",
|
|
+
|
|
+ .base_reg = REG_SPI_CLK_DIV_SEL,
|
|
+
|
|
+ .base_value = 400000000,
|
|
+
|
|
+ .div_bits = 5,
|
|
+ .div_shift = 8,
|
|
+ .div_val0 = 40,
|
|
+ .div_step = 2,
|
|
+ }, {
|
|
+ .id = EN7523_CLK_NPU,
|
|
+ .name = "npu",
|
|
+
|
|
+ .base_reg = REG_NPU_CLK_DIV_SEL,
|
|
+ .base_bits = 2,
|
|
+ .base_shift = 8,
|
|
+ .base_values = npu7581_base,
|
|
+ .n_base_values = ARRAY_SIZE(npu7581_base),
|
|
+
|
|
+ .div_bits = 3,
|
|
+ .div_shift = 0,
|
|
+ .div_step = 1,
|
|
+ .div_offset = 1,
|
|
+ }, {
|
|
+ .id = EN7523_CLK_CRYPTO,
|
|
+ .name = "crypto",
|
|
+
|
|
+ .base_reg = REG_CRYPTO_CLKSRC2,
|
|
+ .base_bits = 1,
|
|
+ .base_shift = 0,
|
|
+ .base_values = crypto_base,
|
|
+ .n_base_values = ARRAY_SIZE(crypto_base),
|
|
+ }
|
|
+};
|
|
+
|
|
static const u16 en7581_rst_ofs[] = {
|
|
REG_RST_CTRL2,
|
|
REG_RST_CTRL1,
|
|
@@ -457,8 +558,8 @@ static void en7581_register_clocks(struc
|
|
u32 rate;
|
|
int i;
|
|
|
|
- for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) {
|
|
- const struct en_clk_desc *desc = &en7523_base_clks[i];
|
|
+ for (i = 0; i < ARRAY_SIZE(en7581_base_clks); i++) {
|
|
+ const struct en_clk_desc *desc = &en7581_base_clks[i];
|
|
u32 val, reg = desc->div_reg ? desc->div_reg : desc->base_reg;
|
|
int err;
|
|
|