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e2e2fc3cd0
Add updated patches for 6.6. DMA/cache-handling patches have been reworked / backported from upstream. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
43 lines
1.3 KiB
Diff
43 lines
1.3 KiB
Diff
From 3e6ea12dda276c01a756764fcafa315b19860c33 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Jo=C3=A3o=20M=C3=A1rio=20Domingos?=
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<joao.mario@tecnico.ulisboa.pt>
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Date: Tue, 16 Nov 2021 15:48:11 +0000
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Subject: [PATCH 075/116] RISC-V: Added generic pmu-events mapfile
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The pmu-events now supports custom events for RISC-V, plus the cycle,
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time and instret events were defined.
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Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
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---
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.../pmu-events/arch/riscv/riscv-generic.json | 20 +++++++++++++++++++
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1 file changed, 20 insertions(+)
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create mode 100644 tools/perf/pmu-events/arch/riscv/riscv-generic.json
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--- /dev/null
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+++ b/tools/perf/pmu-events/arch/riscv/riscv-generic.json
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@@ -0,0 +1,20 @@
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+[
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+ {
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+ "PublicDescription": "CPU Cycles",
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+ "EventCode": "0x00",
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+ "EventName": "riscv_cycles",
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+ "BriefDescription": "CPU cycles RISC-V generic counter"
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+ },
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+ {
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+ "PublicDescription": "CPU Time",
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+ "EventCode": "0x01",
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+ "EventName": "riscv_time",
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+ "BriefDescription": "CPU time RISC-V generic counter"
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+ },
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+ {
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+ "PublicDescription": "CPU Instructions",
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+ "EventCode": "0x02",
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+ "EventName": "riscv_instret",
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+ "BriefDescription": "CPU retired instructions RISC-V generic counter"
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+ }
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+]
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\ No newline at end of file
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