mirror of
https://github.com/openwrt/openwrt.git
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8c405cdccc
The patches were generated from the RPi repo with the following command: git format-patch v6.6.34..rpi-6.1.y Some patches needed rebasing and, as usual, the applied and reverted, wireless drivers, Github workflows, READMEs and defconfigs patches were removed. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
250 lines
7.5 KiB
Diff
250 lines
7.5 KiB
Diff
From fe8bc8bf3e9a9145390dc87dd2ad42f7e8cdfac5 Mon Sep 17 00:00:00 2001
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From: Phil Elwell <phil@raspberrypi.com>
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Date: Fri, 28 Oct 2022 14:10:34 +0100
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Subject: [PATCH 0525/1085] dt-binding: mfd: Add binding for Raspberry Pi RP1
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Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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---
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include/dt-bindings/mfd/rp1.h | 235 ++++++++++++++++++++++++++++++++++
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1 file changed, 235 insertions(+)
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create mode 100644 include/dt-bindings/mfd/rp1.h
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--- /dev/null
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+++ b/include/dt-bindings/mfd/rp1.h
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@@ -0,0 +1,235 @@
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+/* SPDX-License-Identifier: GPL-2.0 */
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+/*
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+ * This header provides constants for the PY MFD.
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+ */
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+
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+#ifndef _RP1_H
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+#define _RP1_H
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+
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+/* Address map */
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+#define RP1_SYSINFO_BASE 0x000000
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+#define RP1_TBMAN_BASE 0x004000
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+#define RP1_SYSCFG_BASE 0x008000
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+#define RP1_OTP_BASE 0x00c000
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+#define RP1_POWER_BASE 0x010000
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+#define RP1_RESETS_BASE 0x014000
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+#define RP1_CLOCKS_BANK_DEFAULT_BASE 0x018000
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+#define RP1_CLOCKS_BANK_VIDEO_BASE 0x01c000
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+#define RP1_PLL_SYS_BASE 0x020000
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+#define RP1_PLL_AUDIO_BASE 0x024000
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+#define RP1_PLL_VIDEO_BASE 0x028000
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+#define RP1_UART0_BASE 0x030000
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+#define RP1_UART1_BASE 0x034000
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+#define RP1_UART2_BASE 0x038000
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+#define RP1_UART3_BASE 0x03c000
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+#define RP1_UART4_BASE 0x040000
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+#define RP1_UART5_BASE 0x044000
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+#define RP1_SPI8_BASE 0x04c000
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+#define RP1_SPI0_BASE 0x050000
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+#define RP1_SPI1_BASE 0x054000
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+#define RP1_SPI2_BASE 0x058000
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+#define RP1_SPI3_BASE 0x05c000
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+#define RP1_SPI4_BASE 0x060000
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+#define RP1_SPI5_BASE 0x064000
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+#define RP1_SPI6_BASE 0x068000
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+#define RP1_SPI7_BASE 0x06c000
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+#define RP1_I2C0_BASE 0x070000
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+#define RP1_I2C1_BASE 0x074000
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+#define RP1_I2C2_BASE 0x078000
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+#define RP1_I2C3_BASE 0x07c000
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+#define RP1_I2C4_BASE 0x080000
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+#define RP1_I2C5_BASE 0x084000
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+#define RP1_I2C6_BASE 0x088000
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+#define RP1_AUDIO_IN_BASE 0x090000
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+#define RP1_AUDIO_OUT_BASE 0x094000
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+#define RP1_PWM0_BASE 0x098000
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+#define RP1_PWM1_BASE 0x09c000
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+#define RP1_I2S0_BASE 0x0a0000
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+#define RP1_I2S1_BASE 0x0a4000
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+#define RP1_I2S2_BASE 0x0a8000
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+#define RP1_TIMER_BASE 0x0ac000
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+#define RP1_SDIO0_APBS_BASE 0x0b0000
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+#define RP1_SDIO1_APBS_BASE 0x0b4000
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+#define RP1_BUSFABRIC_MONITOR_BASE 0x0c0000
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+#define RP1_BUSFABRIC_AXISHIM_BASE 0x0c4000
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+#define RP1_ADC_BASE 0x0c8000
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+#define RP1_IO_BANK0_BASE 0x0d0000
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+#define RP1_IO_BANK1_BASE 0x0d4000
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+#define RP1_IO_BANK2_BASE 0x0d8000
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+#define RP1_SYS_RIO0_BASE 0x0e0000
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+#define RP1_SYS_RIO1_BASE 0x0e4000
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+#define RP1_SYS_RIO2_BASE 0x0e8000
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+#define RP1_PADS_BANK0_BASE 0x0f0000
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+#define RP1_PADS_BANK1_BASE 0x0f4000
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+#define RP1_PADS_BANK2_BASE 0x0f8000
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+#define RP1_PADS_ETH_BASE 0x0fc000
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+#define RP1_ETH_IP_BASE 0x100000
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+#define RP1_ETH_CFG_BASE 0x104000
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+#define RP1_PCIE_APBS_BASE 0x108000
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+#define RP1_MIPI0_CSIDMA_BASE 0x110000
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+#define RP1_MIPI0_CSIHOST_BASE 0x114000
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+#define RP1_MIPI0_DSIDMA_BASE 0x118000
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+#define RP1_MIPI0_DSIHOST_BASE 0x11c000
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+#define RP1_MIPI0_MIPICFG_BASE 0x120000
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+#define RP1_MIPI0_ISP_BASE 0x124000
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+#define RP1_MIPI1_CSIDMA_BASE 0x128000
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+#define RP1_MIPI1_CSIHOST_BASE 0x12c000
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+#define RP1_MIPI1_DSIDMA_BASE 0x130000
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+#define RP1_MIPI1_DSIHOST_BASE 0x134000
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+#define RP1_MIPI1_MIPICFG_BASE 0x138000
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+#define RP1_MIPI1_ISP_BASE 0x13c000
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+#define RP1_VIDEO_OUT_CFG_BASE 0x140000
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+#define RP1_VIDEO_OUT_VEC_BASE 0x144000
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+#define RP1_VIDEO_OUT_DPI_BASE 0x148000
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+#define RP1_XOSC_BASE 0x150000
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+#define RP1_WATCHDOG_BASE 0x154000
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+#define RP1_DMA_TICK_BASE 0x158000
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+#define RP1_SDIO_CLOCKS_BASE 0x15c000
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+#define RP1_USBHOST0_APBS_BASE 0x160000
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+#define RP1_USBHOST1_APBS_BASE 0x164000
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+#define RP1_ROSC0_BASE 0x168000
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+#define RP1_ROSC1_BASE 0x16c000
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+#define RP1_VBUSCTRL_BASE 0x170000
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+#define RP1_TICKS_BASE 0x174000
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+#define RP1_PIO_APBS_BASE 0x178000
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+#define RP1_SDIO0_AHBLS_BASE 0x180000
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+#define RP1_SDIO1_AHBLS_BASE 0x184000
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+#define RP1_DMA_BASE 0x188000
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+#define RP1_RAM_BASE 0x1c0000
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+#define RP1_RAM_SIZE 0x020000
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+#define RP1_USBHOST0_AXIS_BASE 0x200000
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+#define RP1_USBHOST1_AXIS_BASE 0x300000
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+#define RP1_EXAC_BASE 0x400000
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+
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+/* Interrupts */
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+
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+#define RP1_INT_IO_BANK0 0
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+#define RP1_INT_IO_BANK1 1
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+#define RP1_INT_IO_BANK2 2
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+#define RP1_INT_AUDIO_IN 3
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+#define RP1_INT_AUDIO_OUT 4
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+#define RP1_INT_PWM0 5
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+#define RP1_INT_ETH 6
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+#define RP1_INT_I2C0 7
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+#define RP1_INT_I2C1 8
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+#define RP1_INT_I2C2 9
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+#define RP1_INT_I2C3 10
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+#define RP1_INT_I2C4 11
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+#define RP1_INT_I2C5 12
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+#define RP1_INT_I2C6 13
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+#define RP1_INT_I2S0 14
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+#define RP1_INT_I2S1 15
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+#define RP1_INT_I2S2 16
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+#define RP1_INT_SDIO0 17
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+#define RP1_INT_SDIO1 18
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+#define RP1_INT_SPI0 19
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+#define RP1_INT_SPI1 20
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+#define RP1_INT_SPI2 21
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+#define RP1_INT_SPI3 22
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+#define RP1_INT_SPI4 23
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+#define RP1_INT_SPI5 24
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+#define RP1_INT_UART0 25
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+#define RP1_INT_TIMER_0 26
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+#define RP1_INT_TIMER_1 27
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+#define RP1_INT_TIMER_2 28
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+#define RP1_INT_TIMER_3 29
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+#define RP1_INT_USBHOST0 30
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+#define RP1_INT_USBHOST0_0 31
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+#define RP1_INT_USBHOST0_1 32
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+#define RP1_INT_USBHOST0_2 33
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+#define RP1_INT_USBHOST0_3 34
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+#define RP1_INT_USBHOST1 35
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+#define RP1_INT_USBHOST1_0 36
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+#define RP1_INT_USBHOST1_1 37
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+#define RP1_INT_USBHOST1_2 38
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+#define RP1_INT_USBHOST1_3 39
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+#define RP1_INT_DMA 40
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+#define RP1_INT_PWM1 41
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+#define RP1_INT_UART1 42
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+#define RP1_INT_UART2 43
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+#define RP1_INT_UART3 44
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+#define RP1_INT_UART4 45
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+#define RP1_INT_UART5 46
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+#define RP1_INT_MIPI0 47
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+#define RP1_INT_MIPI1 48
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+#define RP1_INT_VIDEO_OUT 49
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+#define RP1_INT_PIO_0 50
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+#define RP1_INT_PIO_1 51
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+#define RP1_INT_ADC_FIFO 52
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+#define RP1_INT_PCIE_OUT 53
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+#define RP1_INT_SPI6 54
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+#define RP1_INT_SPI7 55
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+#define RP1_INT_SPI8 56
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+#define RP1_INT_SYSCFG 58
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+#define RP1_INT_CLOCKS_DEFAULT 59
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+#define RP1_INT_VBUSCTRL 60
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+#define RP1_INT_PROC_MISC 57
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+#define RP1_INT_END 61
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+
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+/* DMA peripherals (for pacing) */
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+#define RP1_DMA_I2C0_RX 0x0
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+#define RP1_DMA_I2C0_TX 0x1
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+#define RP1_DMA_I2C1_RX 0x2
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+#define RP1_DMA_I2C1_TX 0x3
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+#define RP1_DMA_I2C2_RX 0x4
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+#define RP1_DMA_I2C2_TX 0x5
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+#define RP1_DMA_I2C3_RX 0x6
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+#define RP1_DMA_I2C3_TX 0x7
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+#define RP1_DMA_I2C4_RX 0x8
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+#define RP1_DMA_I2C4_TX 0x9
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+#define RP1_DMA_I2C5_RX 0xa
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+#define RP1_DMA_I2C5_TX 0xb
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+#define RP1_DMA_SPI0_RX 0xc
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+#define RP1_DMA_SPI0_TX 0xd
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+#define RP1_DMA_SPI1_RX 0xe
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+#define RP1_DMA_SPI1_TX 0xf
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+#define RP1_DMA_SPI2_RX 0x10
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+#define RP1_DMA_SPI2_TX 0x11
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+#define RP1_DMA_SPI3_RX 0x12
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+#define RP1_DMA_SPI3_TX 0x13
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+#define RP1_DMA_SPI4_RX 0x14
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+#define RP1_DMA_SPI4_TX 0x15
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+#define RP1_DMA_SPI5_RX 0x16
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+#define RP1_DMA_SPI5_TX 0x17
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+#define RP1_DMA_PWM0 0x18
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+#define RP1_DMA_UART0_RX 0x19
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+#define RP1_DMA_UART0_TX 0x1a
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+#define RP1_DMA_AUDIO_IN_CH0 0x1b
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+#define RP1_DMA_AUDIO_IN_CH1 0x1c
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+#define RP1_DMA_AUDIO_OUT 0x1d
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+#define RP1_DMA_PWM1 0x1e
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+#define RP1_DMA_I2S0_RX 0x1f
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+#define RP1_DMA_I2S0_TX 0x20
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+#define RP1_DMA_I2S1_RX 0x21
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+#define RP1_DMA_I2S1_TX 0x22
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+#define RP1_DMA_I2S2_RX 0x23
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+#define RP1_DMA_I2S2_TX 0x24
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+#define RP1_DMA_UART1_RX 0x25
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+#define RP1_DMA_UART1_TX 0x26
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+#define RP1_DMA_UART2_RX 0x27
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+#define RP1_DMA_UART2_TX 0x28
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+#define RP1_DMA_UART3_RX 0x29
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+#define RP1_DMA_UART3_TX 0x2a
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+#define RP1_DMA_UART4_RX 0x2b
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+#define RP1_DMA_UART4_TX 0x2c
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+#define RP1_DMA_UART5_RX 0x2d
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+#define RP1_DMA_UART5_TX 0x2e
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+#define RP1_DMA_ADC 0x2f
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+#define RP1_DMA_DMA_TICK_TICK0 0x30
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+#define RP1_DMA_DMA_TICK_TICK1 0x31
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+#define RP1_DMA_SPI6_RX 0x32
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+#define RP1_DMA_SPI6_TX 0x33
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+#define RP1_DMA_SPI7_RX 0x34
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+#define RP1_DMA_SPI7_TX 0x35
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+#define RP1_DMA_SPI8_RX 0x36
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+#define RP1_DMA_SPI8_TX 0x37
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+#define RP1_DMA_PIO_CH0_TX 0x38
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+#define RP1_DMA_PIO_CH0_RX 0x39
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+#define RP1_DMA_PIO_CH1_TX 0x3a
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+#define RP1_DMA_PIO_CH1_RX 0x3b
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+#define RP1_DMA_PIO_CH2_TX 0x3c
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+#define RP1_DMA_PIO_CH2_RX 0x3d
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+#define RP1_DMA_PIO_CH3_TX 0x3e
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+#define RP1_DMA_PIO_CH3_RX 0x3f
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+
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+#endif
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