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220860ef4c
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.6.70
Removed upstreamed:
generic/backport-6.6/902-net-llc-reset-skb-transport_header.patch[1]
generic/pending-6.6/605-netfilter-nft_set_hash-unaligned-atomic-read-on-stru.patch[2]
All other patches automatically rebased.
1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.70&id=0c896816aa193e6459fc947747e5753c06b395b9
2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.70&id=4f49349c1963e507aa37c1ec05178faeb0103959
Build system: x86/64
Build-tested: bcm27xx/bcm2712, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3
Run-tested: bcm27xx/bcm2712, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3
Signed-off-by: John Audia <therealgraysky@proton.me>
Link: https://github.com/openwrt/openwrt/pull/17545
Signed-off-by: Robert Marko <robimarko@gmail.com>
(cherry picked from commit efafd7d47f)
92 lines
2.7 KiB
Diff
92 lines
2.7 KiB
Diff
From 97789b93b792fc97ad4476b79e0f38ffa8e7e0ee Mon Sep 17 00:00:00 2001
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From: Sebastian Reichel <sebastian.reichel@collabora.com>
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Date: Fri, 20 Oct 2023 16:11:41 +0200
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Subject: [PATCH] usb: dwc3: add optional PHY interface clocks
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On Rockchip RK3588 one of the DWC3 cores is integrated weirdly and
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requires two extra clocks to be enabled. Without these extra clocks
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hot-plugging USB devices is broken.
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Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
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Link: https://lore.kernel.org/r/20231020150022.48725-3-sebastian.reichel@collabora.com
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Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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---
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drivers/usb/dwc3/core.c | 28 ++++++++++++++++++++++++++++
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drivers/usb/dwc3/core.h | 4 ++++
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2 files changed, 32 insertions(+)
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--- a/drivers/usb/dwc3/core.c
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+++ b/drivers/usb/dwc3/core.c
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@@ -845,8 +845,20 @@ static int dwc3_clk_enable(struct dwc3 *
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if (ret)
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goto disable_ref_clk;
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+ ret = clk_prepare_enable(dwc->utmi_clk);
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+ if (ret)
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+ goto disable_susp_clk;
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+
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+ ret = clk_prepare_enable(dwc->pipe_clk);
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+ if (ret)
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+ goto disable_utmi_clk;
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+
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return 0;
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+disable_utmi_clk:
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+ clk_disable_unprepare(dwc->utmi_clk);
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+disable_susp_clk:
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+ clk_disable_unprepare(dwc->susp_clk);
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disable_ref_clk:
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clk_disable_unprepare(dwc->ref_clk);
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disable_bus_clk:
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@@ -856,6 +868,8 @@ disable_bus_clk:
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static void dwc3_clk_disable(struct dwc3 *dwc)
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{
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+ clk_disable_unprepare(dwc->pipe_clk);
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+ clk_disable_unprepare(dwc->utmi_clk);
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clk_disable_unprepare(dwc->susp_clk);
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clk_disable_unprepare(dwc->ref_clk);
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clk_disable_unprepare(dwc->bus_clk);
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@@ -1884,6 +1898,20 @@ static int dwc3_get_clocks(struct dwc3 *
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}
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}
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+ /* specific to Rockchip RK3588 */
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+ dwc->utmi_clk = devm_clk_get_optional(dev, "utmi");
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+ if (IS_ERR(dwc->utmi_clk)) {
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+ return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk),
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+ "could not get utmi clock\n");
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+ }
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+
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+ /* specific to Rockchip RK3588 */
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+ dwc->pipe_clk = devm_clk_get_optional(dev, "pipe");
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+ if (IS_ERR(dwc->pipe_clk)) {
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+ return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk),
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+ "could not get pipe clock\n");
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+ }
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+
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return 0;
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}
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--- a/drivers/usb/dwc3/core.h
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+++ b/drivers/usb/dwc3/core.h
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@@ -1002,6 +1002,8 @@ struct dwc3_scratchpad_array {
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* @bus_clk: clock for accessing the registers
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* @ref_clk: reference clock
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* @susp_clk: clock used when the SS phy is in low power (S3) state
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+ * @utmi_clk: clock used for USB2 PHY communication
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+ * @pipe_clk: clock used for USB3 PHY communication
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* @reset: reset control
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* @regs: base address for our registers
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* @regs_size: address space size
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@@ -1174,6 +1176,8 @@ struct dwc3 {
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struct clk *bus_clk;
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struct clk *ref_clk;
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struct clk *susp_clk;
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+ struct clk *utmi_clk;
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+ struct clk *pipe_clk;
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struct reset_control *reset;
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