mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-25 00:11:13 +00:00
4e39949dd1
Removed since could be reverse-applied by quilt and found to be included upstream: backport-5.4/789-net-usb-qmi_wwan-Set-DTR-quirk-for-MR400.patch All modifications made by update_kernel.sh Build system: x86_64 Build-tested: ipq806x/R7800, bcm27xx/bcm2711, ath79/generic Run-tested: ipq806x/R7800 No dmesg regressions, everything functional Signed-off-by: John Audia <graysky@archlinux.us> Tested-by: Curtis Deptuck <curtdept@me.com> [x86_64 build/run]
108 lines
3.7 KiB
Diff
108 lines
3.7 KiB
Diff
From 6adf87956ee1043e6bf0ef83fa0eec1e755c0d48 Mon Sep 17 00:00:00 2001
|
|
From: Marc Kleine-Budde <mkl@pengutronix.de>
|
|
Date: Fri, 1 Mar 2019 12:17:30 +0100
|
|
Subject: [PATCH] can: flexcan: convert struct flexcan_priv::rx_mask{1,2} to
|
|
rx_mask
|
|
|
|
The flexcan IP core has up to 64 mailboxes, each one has a corresponding
|
|
interrupt bit in the iflag1 or iflag2 registers and a mask bit in the
|
|
imask1 or imask2 registers.
|
|
|
|
In the timestamp (i.e. non FIFO) mode the driver needs to mask out all non RX
|
|
interrupt sources and uses the precomputed values rx_mask1 and rx_mask2 of
|
|
struct flexcan_priv for this.
|
|
|
|
This patch merges the two u32 rx_mask1 and rx_mask2 to a single u64 rx_mask
|
|
variable, which simplifies the code a bit.
|
|
|
|
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
|
|
---
|
|
drivers/net/can/flexcan.c | 30 +++++++++++++-----------------
|
|
1 file changed, 13 insertions(+), 17 deletions(-)
|
|
|
|
--- a/drivers/net/can/flexcan.c
|
|
+++ b/drivers/net/can/flexcan.c
|
|
@@ -142,6 +142,7 @@
|
|
#define FLEXCAN_TX_MB_RESERVED_OFF_FIFO 8
|
|
#define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP 0
|
|
#define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST (FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP + 1)
|
|
+#define FLEXCAN_IFLAG_MB(x) BIT_ULL(x)
|
|
#define FLEXCAN_IFLAG2_MB(x) BIT((x) & 0x1f)
|
|
#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
|
|
#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
|
|
@@ -277,9 +278,8 @@ struct flexcan_priv {
|
|
u8 mb_size;
|
|
u8 clk_src; /* clock source of CAN Protocol Engine */
|
|
|
|
+ u64 rx_mask;
|
|
u32 reg_ctrl_default;
|
|
- u32 rx_mask1;
|
|
- u32 rx_mask2;
|
|
|
|
struct clk *clk_ipg;
|
|
struct clk *clk_per;
|
|
@@ -874,16 +874,15 @@ static struct sk_buff *flexcan_mailbox_r
|
|
return skb;
|
|
}
|
|
|
|
-
|
|
static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
|
|
{
|
|
struct flexcan_regs __iomem *regs = priv->regs;
|
|
- u32 iflag1, iflag2;
|
|
+ u64 iflag;
|
|
|
|
- iflag2 = priv->read(®s->iflag2) & priv->rx_mask2;
|
|
- iflag1 = priv->read(®s->iflag1) & priv->rx_mask1;
|
|
+ iflag = (u64)priv->read(®s->iflag2) << 32 |
|
|
+ priv->read(®s->iflag1);
|
|
|
|
- return (u64)iflag2 << 32 | iflag1;
|
|
+ return iflag & priv->rx_mask;
|
|
}
|
|
|
|
static irqreturn_t flexcan_irq(int irq, void *dev_id)
|
|
@@ -1054,6 +1053,7 @@ static int flexcan_chip_start(struct net
|
|
struct flexcan_priv *priv = netdev_priv(dev);
|
|
struct flexcan_regs __iomem *regs = priv->regs;
|
|
u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
|
|
+ u64 reg_imask;
|
|
int err, i;
|
|
struct flexcan_mb __iomem *mb;
|
|
|
|
@@ -1224,8 +1224,9 @@ static int flexcan_chip_start(struct net
|
|
/* enable interrupts atomically */
|
|
disable_irq(dev->irq);
|
|
priv->write(priv->reg_ctrl_default, ®s->ctrl);
|
|
- priv->write(priv->rx_mask1, ®s->imask1);
|
|
- priv->write(priv->rx_mask2 | FLEXCAN_IFLAG2_MB(priv->tx_mb_idx), ®s->imask2);
|
|
+ reg_imask = priv->rx_mask | FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
|
|
+ priv->write(upper_32_bits(reg_imask), ®s->imask2);
|
|
+ priv->write(lower_32_bits(reg_imask), ®s->imask1);
|
|
enable_irq(dev->irq);
|
|
|
|
/* print chip status */
|
|
@@ -1322,19 +1323,14 @@ static int flexcan_open(struct net_devic
|
|
priv->offload.mailbox_read = flexcan_mailbox_read;
|
|
|
|
if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
|
|
- u64 imask;
|
|
-
|
|
priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST;
|
|
priv->offload.mb_last = priv->mb_count - 2;
|
|
|
|
- imask = GENMASK_ULL(priv->offload.mb_last,
|
|
- priv->offload.mb_first);
|
|
- priv->rx_mask1 = imask;
|
|
- priv->rx_mask2 = imask >> 32;
|
|
-
|
|
+ priv->rx_mask = GENMASK_ULL(priv->offload.mb_last,
|
|
+ priv->offload.mb_first);
|
|
err = can_rx_offload_add_timestamp(dev, &priv->offload);
|
|
} else {
|
|
- priv->rx_mask1 = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
|
|
+ priv->rx_mask = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
|
|
FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
|
|
err = can_rx_offload_add_fifo(dev, &priv->offload,
|
|
FLEXCAN_NAPI_WEIGHT);
|