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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
52 lines
1.8 KiB
Diff
52 lines
1.8 KiB
Diff
From f7fb35d540240889a8f45f3fd42363cbc1a448e2 Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Fri, 19 Aug 2022 00:06:20 +0200
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Subject: [PATCH] clk: qcom: clk-rcg2: add rcg2 mux ops
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An RCG may act as a mux that switch between 2 parents.
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This is the case on IPQ6018 and IPQ8074 where the APCS core clk that feeds
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the CPU cluster clock just switches between XO and the PLL that feeds it.
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Add the required ops to add support for this special configuration and use
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the generic mux function to determine the rate.
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This way we dont have to keep a essentially dummy frequency table to use
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RCG2 as a mux.
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Link: https://lore.kernel.org/r/20220818220628.339366-1-robimarko@gmail.com
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---
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drivers/clk/qcom/clk-rcg.h | 1 +
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drivers/clk/qcom/clk-rcg2.c | 7 +++++++
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2 files changed, 8 insertions(+)
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--- a/drivers/clk/qcom/clk-rcg.h
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+++ b/drivers/clk/qcom/clk-rcg.h
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@@ -164,6 +164,7 @@ struct clk_rcg2_gfx3d {
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extern const struct clk_ops clk_rcg2_ops;
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extern const struct clk_ops clk_rcg2_floor_ops;
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+extern const struct clk_ops clk_rcg2_mux_closest_ops;
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extern const struct clk_ops clk_edp_pixel_ops;
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extern const struct clk_ops clk_byte_ops;
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extern const struct clk_ops clk_byte2_ops;
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--- a/drivers/clk/qcom/clk-rcg2.c
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+++ b/drivers/clk/qcom/clk-rcg2.c
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@@ -477,6 +477,13 @@ const struct clk_ops clk_rcg2_floor_ops
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};
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EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops);
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+const struct clk_ops clk_rcg2_mux_closest_ops = {
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+ .determine_rate = __clk_mux_determine_rate_closest,
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+ .get_parent = clk_rcg2_get_parent,
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+ .set_parent = clk_rcg2_set_parent,
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+};
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+EXPORT_SYMBOL_GPL(clk_rcg2_mux_closest_ops);
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+
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struct frac_entry {
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int num;
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int den;
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