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0a827ebd2f
This patch is to upgrade kernel to 4.14 for layerscape. patches-4.14 for layerscape included two categories. - NXP Layerscape SDK kernel-4.14 patches All patches on tag LSDK-18.09-V4.14 were ported to OpenWrt kernel. Since there were hundreds patches, we had to make an all-in-one patch for each IP/feature. See below links for LSDK kernel. https://lsdk.github.io/components.html https://source.codeaurora.org/external/qoriq/qoriq-components/linux - Non-LSDK kernel patches Other patches which were not in LSDK were just put in patches-4.14. Kept below patches from patches-4.9. 303-dts-layerscape-add-traverse-ls1043.patch 821-add-esdhc-vsel-to-ls1043.patch 822-rgmii-fixed-link.patch Renamed and rebase them as below in patches-4.14, 303-add-DTS-for-Traverse-LS1043-Boards.patch 712-sdk-dpaa-rgmii-fixed-link.patch 824-mmc-sdhci-of-esdhc-add-voltage-switch-support-for-ls.patch Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Biwen Li <biwen.li@nxp.com>
551 lines
16 KiB
Diff
551 lines
16 KiB
Diff
From 48dbe4b3a31795b8efdfff82f69eccd086052eed Mon Sep 17 00:00:00 2001
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From: Biwen Li <biwen.li@nxp.com>
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Date: Fri, 16 Nov 2018 10:27:30 +0800
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Subject: [PATCH 16/39] dpaa-bqman: support layerscape
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This is an integrated patch of dpaa-bqman for layerscape
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Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
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Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
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Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
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Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
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Signed-off-by: Valentin Rothberg <valentinrothberg@gmail.com>
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Signed-off-by: Biwen Li <biwen.li@nxp.com>
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---
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drivers/soc/fsl/qbman/Kconfig | 2 +-
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drivers/soc/fsl/qbman/bman.c | 24 ++++-
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drivers/soc/fsl/qbman/bman_ccsr.c | 35 ++++++-
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drivers/soc/fsl/qbman/bman_portal.c | 12 ++-
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drivers/soc/fsl/qbman/bman_priv.h | 3 +
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drivers/soc/fsl/qbman/dpaa_sys.h | 8 +-
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drivers/soc/fsl/qbman/qman.c | 46 ++++++++-
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drivers/soc/fsl/qbman/qman_ccsr.c | 140 ++++++++++++++++++++++------
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drivers/soc/fsl/qbman/qman_portal.c | 12 ++-
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drivers/soc/fsl/qbman/qman_priv.h | 5 +-
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drivers/soc/fsl/qbman/qman_test.h | 2 -
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11 files changed, 236 insertions(+), 53 deletions(-)
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--- a/drivers/soc/fsl/qbman/Kconfig
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+++ b/drivers/soc/fsl/qbman/Kconfig
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@@ -1,6 +1,6 @@
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menuconfig FSL_DPAA
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bool "Freescale DPAA 1.x support"
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- depends on FSL_SOC_BOOKE
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+ depends on (FSL_SOC_BOOKE || ARCH_LAYERSCAPE)
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select GENERIC_ALLOCATOR
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help
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The Freescale Data Path Acceleration Architecture (DPAA) is a set of
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--- a/drivers/soc/fsl/qbman/bman.c
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+++ b/drivers/soc/fsl/qbman/bman.c
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@@ -35,6 +35,27 @@
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/* Portal register assists */
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+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
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+/* Cache-inhibited register offsets */
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+#define BM_REG_RCR_PI_CINH 0x3000
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+#define BM_REG_RCR_CI_CINH 0x3100
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+#define BM_REG_RCR_ITR 0x3200
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+#define BM_REG_CFG 0x3300
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+#define BM_REG_SCN(n) (0x3400 + ((n) << 6))
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+#define BM_REG_ISR 0x3e00
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+#define BM_REG_IER 0x3e40
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+#define BM_REG_ISDR 0x3e80
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+#define BM_REG_IIR 0x3ec0
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+
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+/* Cache-enabled register offsets */
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+#define BM_CL_CR 0x0000
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+#define BM_CL_RR0 0x0100
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+#define BM_CL_RR1 0x0140
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+#define BM_CL_RCR 0x1000
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+#define BM_CL_RCR_PI_CENA 0x3000
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+#define BM_CL_RCR_CI_CENA 0x3100
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+
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+#else
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/* Cache-inhibited register offsets */
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#define BM_REG_RCR_PI_CINH 0x0000
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#define BM_REG_RCR_CI_CINH 0x0004
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@@ -53,6 +74,7 @@
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#define BM_CL_RCR 0x1000
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#define BM_CL_RCR_PI_CENA 0x3000
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#define BM_CL_RCR_CI_CENA 0x3100
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+#endif
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/*
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* Portal modes.
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@@ -607,7 +629,7 @@ int bman_p_irqsource_add(struct bman_por
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unsigned long irqflags;
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local_irq_save(irqflags);
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- set_bits(bits & BM_PIRQ_VISIBLE, &p->irq_sources);
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+ p->irq_sources |= bits & BM_PIRQ_VISIBLE;
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bm_out(&p->p, BM_REG_IER, p->irq_sources);
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local_irq_restore(irqflags);
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return 0;
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--- a/drivers/soc/fsl/qbman/bman_ccsr.c
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+++ b/drivers/soc/fsl/qbman/bman_ccsr.c
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@@ -170,10 +170,11 @@ static int fsl_bman_probe(struct platfor
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{
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int ret, err_irq;
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struct device *dev = &pdev->dev;
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- struct device_node *node = dev->of_node;
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+ struct device_node *mem_node, *node = dev->of_node;
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struct resource *res;
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u16 id, bm_pool_cnt;
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u8 major, minor;
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+ u64 size;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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@@ -201,6 +202,38 @@ static int fsl_bman_probe(struct platfor
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return -ENODEV;
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}
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+ /*
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+ * If FBPR memory wasn't defined using the qbman compatiable string
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+ * try using the of_reserved_mem_device method
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+ */
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+ if (!fbpr_a) {
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+ ret = of_reserved_mem_device_init(dev);
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+ if (ret) {
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+ dev_err(dev, "of_reserved_mem_device_init() failed 0x%x\n",
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+ ret);
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+ return -ENODEV;
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+ }
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+ mem_node = of_parse_phandle(dev->of_node, "memory-region", 0);
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+ if (mem_node) {
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+ ret = of_property_read_u64(mem_node, "size", &size);
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+ if (ret) {
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+ dev_err(dev, "FBPR: of_address_to_resource fails 0x%x\n",
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+ ret);
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+ return -ENODEV;
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+ }
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+ fbpr_sz = size;
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+ } else {
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+ dev_err(dev, "No memory-region found for FBPR\n");
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+ return -ENODEV;
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+ }
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+ if (!dma_zalloc_coherent(dev, fbpr_sz, &fbpr_a, 0)) {
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+ dev_err(dev, "Alloc FBPR memory failed\n");
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+ return -ENODEV;
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+ }
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+ }
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+
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+ dev_dbg(dev, "Allocated FBPR 0x%llx 0x%zx\n", fbpr_a, fbpr_sz);
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+
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bm_set_memory(fbpr_a, fbpr_sz);
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err_irq = platform_get_irq(pdev, 0);
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--- a/drivers/soc/fsl/qbman/bman_portal.c
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+++ b/drivers/soc/fsl/qbman/bman_portal.c
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@@ -123,7 +123,14 @@ static int bman_portal_probe(struct plat
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}
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pcfg->irq = irq;
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- va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]), 0);
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+#ifdef CONFIG_PPC
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+ /* PPC requires a cacheable/non-coherent mapping of the portal */
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+ va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]),
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+ (pgprot_val(PAGE_KERNEL) & ~_PAGE_COHERENT));
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+#else
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+ /* For ARM we can use write combine mapping. */
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+ va = ioremap_wc(addr_phys[0]->start, resource_size(addr_phys[0]));
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+#endif
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if (!va) {
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dev_err(dev, "ioremap::CE failed\n");
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goto err_ioremap1;
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@@ -131,8 +138,7 @@ static int bman_portal_probe(struct plat
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pcfg->addr_virt[DPAA_PORTAL_CE] = va;
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- va = ioremap_prot(addr_phys[1]->start, resource_size(addr_phys[1]),
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- _PAGE_GUARDED | _PAGE_NO_CACHE);
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+ va = ioremap(addr_phys[1]->start, resource_size(addr_phys[1]));
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if (!va) {
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dev_err(dev, "ioremap::CI failed\n");
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goto err_ioremap2;
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--- a/drivers/soc/fsl/qbman/bman_priv.h
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+++ b/drivers/soc/fsl/qbman/bman_priv.h
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@@ -33,6 +33,9 @@
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#include "dpaa_sys.h"
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#include <soc/fsl/bman.h>
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+#include <linux/dma-contiguous.h>
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+#include <linux/of_address.h>
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+#include <linux/dma-mapping.h>
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/* Portal processing (interrupt) sources */
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#define BM_PIRQ_RCRI 0x00000002 /* RCR Ring (below threshold) */
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--- a/drivers/soc/fsl/qbman/dpaa_sys.h
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+++ b/drivers/soc/fsl/qbman/dpaa_sys.h
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@@ -44,20 +44,18 @@
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#include <linux/prefetch.h>
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#include <linux/genalloc.h>
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#include <asm/cacheflush.h>
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+#include <linux/io.h>
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+#include <linux/delay.h>
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/* For 2-element tables related to cache-inhibited and cache-enabled mappings */
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#define DPAA_PORTAL_CE 0
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#define DPAA_PORTAL_CI 1
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-#if (L1_CACHE_BYTES != 32) && (L1_CACHE_BYTES != 64)
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-#error "Unsupported Cacheline Size"
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-#endif
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-
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static inline void dpaa_flush(void *p)
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{
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#ifdef CONFIG_PPC
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flush_dcache_range((unsigned long)p, (unsigned long)p+64);
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-#elif defined(CONFIG_ARM32)
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+#elif defined(CONFIG_ARM)
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__cpuc_flush_dcache_area(p, 64);
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#elif defined(CONFIG_ARM64)
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__flush_dcache_area(p, 64);
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--- a/drivers/soc/fsl/qbman/qman.c
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+++ b/drivers/soc/fsl/qbman/qman.c
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@@ -41,6 +41,43 @@
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/* Portal register assists */
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+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
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+/* Cache-inhibited register offsets */
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+#define QM_REG_EQCR_PI_CINH 0x3000
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+#define QM_REG_EQCR_CI_CINH 0x3040
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+#define QM_REG_EQCR_ITR 0x3080
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+#define QM_REG_DQRR_PI_CINH 0x3100
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+#define QM_REG_DQRR_CI_CINH 0x3140
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+#define QM_REG_DQRR_ITR 0x3180
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+#define QM_REG_DQRR_DCAP 0x31C0
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+#define QM_REG_DQRR_SDQCR 0x3200
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+#define QM_REG_DQRR_VDQCR 0x3240
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+#define QM_REG_DQRR_PDQCR 0x3280
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+#define QM_REG_MR_PI_CINH 0x3300
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+#define QM_REG_MR_CI_CINH 0x3340
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+#define QM_REG_MR_ITR 0x3380
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+#define QM_REG_CFG 0x3500
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+#define QM_REG_ISR 0x3600
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+#define QM_REG_IER 0x3640
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+#define QM_REG_ISDR 0x3680
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+#define QM_REG_IIR 0x36C0
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+#define QM_REG_ITPR 0x3740
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+
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+/* Cache-enabled register offsets */
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+#define QM_CL_EQCR 0x0000
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+#define QM_CL_DQRR 0x1000
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+#define QM_CL_MR 0x2000
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+#define QM_CL_EQCR_PI_CENA 0x3000
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+#define QM_CL_EQCR_CI_CENA 0x3040
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+#define QM_CL_DQRR_PI_CENA 0x3100
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+#define QM_CL_DQRR_CI_CENA 0x3140
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+#define QM_CL_MR_PI_CENA 0x3300
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+#define QM_CL_MR_CI_CENA 0x3340
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+#define QM_CL_CR 0x3800
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+#define QM_CL_RR0 0x3900
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+#define QM_CL_RR1 0x3940
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+
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+#else
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/* Cache-inhibited register offsets */
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#define QM_REG_EQCR_PI_CINH 0x0000
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#define QM_REG_EQCR_CI_CINH 0x0004
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@@ -75,6 +112,7 @@
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#define QM_CL_CR 0x3800
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#define QM_CL_RR0 0x3900
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#define QM_CL_RR1 0x3940
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+#endif
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/*
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* BTW, the drivers (and h/w programming model) already obtain the required
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@@ -909,12 +947,12 @@ static inline int qm_mc_result_timeout(s
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static inline void fq_set(struct qman_fq *fq, u32 mask)
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{
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- set_bits(mask, &fq->flags);
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+ fq->flags |= mask;
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}
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static inline void fq_clear(struct qman_fq *fq, u32 mask)
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{
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- clear_bits(mask, &fq->flags);
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+ fq->flags &= ~mask;
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}
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static inline int fq_isset(struct qman_fq *fq, u32 mask)
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@@ -1566,7 +1604,7 @@ void qman_p_irqsource_add(struct qman_po
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unsigned long irqflags;
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local_irq_save(irqflags);
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- set_bits(bits & QM_PIRQ_VISIBLE, &p->irq_sources);
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+ p->irq_sources |= bits & QM_PIRQ_VISIBLE;
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qm_out(&p->p, QM_REG_IER, p->irq_sources);
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local_irq_restore(irqflags);
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}
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@@ -1589,7 +1627,7 @@ void qman_p_irqsource_remove(struct qman
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*/
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local_irq_save(irqflags);
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bits &= QM_PIRQ_VISIBLE;
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- clear_bits(bits, &p->irq_sources);
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+ p->irq_sources &= ~bits;
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qm_out(&p->p, QM_REG_IER, p->irq_sources);
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ier = qm_in(&p->p, QM_REG_IER);
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/*
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--- a/drivers/soc/fsl/qbman/qman_ccsr.c
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+++ b/drivers/soc/fsl/qbman/qman_ccsr.c
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@@ -401,21 +401,42 @@ static int qm_init_pfdr(struct device *d
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}
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/*
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- * Ideally we would use the DMA API to turn rmem->base into a DMA address
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- * (especially if iommu translations ever get involved). Unfortunately, the
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- * DMA API currently does not allow mapping anything that is not backed with
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- * a struct page.
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+ * QMan needs two global memory areas initialized at boot time:
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+ * 1) FQD: Frame Queue Descriptors used to manage frame queues
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+ * 2) PFDR: Packed Frame Queue Descriptor Records used to store frames
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+ * Both areas are reserved using the device tree reserved memory framework
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+ * and the addresses and sizes are initialized when the QMan device is probed
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*/
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static dma_addr_t fqd_a, pfdr_a;
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static size_t fqd_sz, pfdr_sz;
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+#ifdef CONFIG_PPC
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+/*
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+ * Support for PPC Device Tree backward compatibility when compatiable
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+ * string is set to fsl-qman-fqd and fsl-qman-pfdr
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+ */
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+static int zero_priv_mem(phys_addr_t addr, size_t sz)
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+{
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+ /* map as cacheable, non-guarded */
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+ void __iomem *tmpp = ioremap_prot(addr, sz, 0);
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+
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+ if (!tmpp)
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+ return -ENOMEM;
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+
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+ memset_io(tmpp, 0, sz);
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+ flush_dcache_range((unsigned long)tmpp,
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+ (unsigned long)tmpp + sz);
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+ iounmap(tmpp);
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+
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+ return 0;
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+}
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+
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static int qman_fqd(struct reserved_mem *rmem)
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{
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fqd_a = rmem->base;
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fqd_sz = rmem->size;
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WARN_ON(!(fqd_a && fqd_sz));
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-
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return 0;
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}
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RESERVEDMEM_OF_DECLARE(qman_fqd, "fsl,qman-fqd", qman_fqd);
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@@ -431,32 +452,13 @@ static int qman_pfdr(struct reserved_mem
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}
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RESERVEDMEM_OF_DECLARE(qman_pfdr, "fsl,qman-pfdr", qman_pfdr);
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+#endif
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+
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static unsigned int qm_get_fqid_maxcnt(void)
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{
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return fqd_sz / 64;
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}
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-/*
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- * Flush this memory range from data cache so that QMAN originated
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- * transactions for this memory region could be marked non-coherent.
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- */
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-static int zero_priv_mem(struct device *dev, struct device_node *node,
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- phys_addr_t addr, size_t sz)
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-{
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- /* map as cacheable, non-guarded */
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- void __iomem *tmpp = ioremap_prot(addr, sz, 0);
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-
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- if (!tmpp)
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- return -ENOMEM;
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-
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- memset_io(tmpp, 0, sz);
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- flush_dcache_range((unsigned long)tmpp,
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- (unsigned long)tmpp + sz);
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- iounmap(tmpp);
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-
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- return 0;
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-}
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-
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static void log_edata_bits(struct device *dev, u32 bit_count)
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{
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u32 i, j, mask = 0xffffffff;
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@@ -687,11 +689,12 @@ static int qman_resource_init(struct dev
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static int fsl_qman_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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- struct device_node *node = dev->of_node;
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+ struct device_node *mem_node, *node = dev->of_node;
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struct resource *res;
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int ret, err_irq;
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u16 id;
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u8 major, minor;
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+ u64 size;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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@@ -717,6 +720,8 @@ static int fsl_qman_probe(struct platfor
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qman_ip_rev = QMAN_REV30;
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else if (major == 3 && minor == 1)
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qman_ip_rev = QMAN_REV31;
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+ else if (major == 3 && minor == 2)
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+ qman_ip_rev = QMAN_REV32;
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else {
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dev_err(dev, "Unknown QMan version\n");
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return -ENODEV;
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|
@@ -727,10 +732,83 @@ static int fsl_qman_probe(struct platfor
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|
qm_channel_caam = QMAN_CHANNEL_CAAM_REV3;
|
|
}
|
|
|
|
- ret = zero_priv_mem(dev, node, fqd_a, fqd_sz);
|
|
- WARN_ON(ret);
|
|
- if (ret)
|
|
- return -ENODEV;
|
|
+ if (fqd_a) {
|
|
+#ifdef CONFIG_PPC
|
|
+ /*
|
|
+ * For PPC backward DT compatibility
|
|
+ * FQD memory MUST be zero'd by software
|
|
+ */
|
|
+ zero_priv_mem(fqd_a, fqd_sz);
|
|
+#else
|
|
+ WARN(1, "Unexpected archiceture using non shared-dma-mem reservations");
|
|
+#endif
|
|
+ } else {
|
|
+ /*
|
|
+ * Order of memory regions is assumed as FQD followed by PFDR
|
|
+ * in order to ensure allocations from the correct regions the
|
|
+ * driver initializes then allocates each piece in order
|
|
+ */
|
|
+ ret = of_reserved_mem_device_init_by_idx(dev, dev->of_node, 0);
|
|
+ if (ret) {
|
|
+ dev_err(dev, "of_reserved_mem_device_init_by_idx(0) failed 0x%x\n",
|
|
+ ret);
|
|
+ return -ENODEV;
|
|
+ }
|
|
+ mem_node = of_parse_phandle(dev->of_node, "memory-region", 0);
|
|
+ if (mem_node) {
|
|
+ ret = of_property_read_u64(mem_node, "size", &size);
|
|
+ if (ret) {
|
|
+ dev_err(dev, "FQD: of_address_to_resource fails 0x%x\n",
|
|
+ ret);
|
|
+ return -ENODEV;
|
|
+ }
|
|
+ fqd_sz = size;
|
|
+ } else {
|
|
+ dev_err(dev, "No memory-region found for FQD\n");
|
|
+ return -ENODEV;
|
|
+ }
|
|
+ if (!dma_zalloc_coherent(dev, fqd_sz, &fqd_a, 0)) {
|
|
+ dev_err(dev, "Alloc FQD memory failed\n");
|
|
+ return -ENODEV;
|
|
+ }
|
|
+
|
|
+ /*
|
|
+ * Disassociate the FQD reserved memory area from the device
|
|
+ * because a device can only have one DMA memory area. This
|
|
+ * should be fine since the memory is allocated and initialized
|
|
+ * and only ever accessed by the QMan device from now on
|
|
+ */
|
|
+ of_reserved_mem_device_release(dev);
|
|
+ }
|
|
+ dev_dbg(dev, "Allocated FQD 0x%llx 0x%zx\n", fqd_a, fqd_sz);
|
|
+
|
|
+ if (!pfdr_a) {
|
|
+ /* Setup PFDR memory */
|
|
+ ret = of_reserved_mem_device_init_by_idx(dev, dev->of_node, 1);
|
|
+ if (ret) {
|
|
+ dev_err(dev, "of_reserved_mem_device_init(1) failed 0x%x\n",
|
|
+ ret);
|
|
+ return -ENODEV;
|
|
+ }
|
|
+ mem_node = of_parse_phandle(dev->of_node, "memory-region", 1);
|
|
+ if (mem_node) {
|
|
+ ret = of_property_read_u64(mem_node, "size", &size);
|
|
+ if (ret) {
|
|
+ dev_err(dev, "PFDR: of_address_to_resource fails 0x%x\n",
|
|
+ ret);
|
|
+ return -ENODEV;
|
|
+ }
|
|
+ pfdr_sz = size;
|
|
+ } else {
|
|
+ dev_err(dev, "No memory-region found for PFDR\n");
|
|
+ return -ENODEV;
|
|
+ }
|
|
+ if (!dma_zalloc_coherent(dev, pfdr_sz, &pfdr_a, 0)) {
|
|
+ dev_err(dev, "Alloc PFDR Failed size 0x%zx\n", pfdr_sz);
|
|
+ return -ENODEV;
|
|
+ }
|
|
+ }
|
|
+ dev_info(dev, "Allocated PFDR 0x%llx 0x%zx\n", pfdr_a, pfdr_sz);
|
|
|
|
ret = qman_init_ccsr(dev);
|
|
if (ret) {
|
|
--- a/drivers/soc/fsl/qbman/qman_portal.c
|
|
+++ b/drivers/soc/fsl/qbman/qman_portal.c
|
|
@@ -262,7 +262,14 @@ static int qman_portal_probe(struct plat
|
|
}
|
|
pcfg->irq = irq;
|
|
|
|
- va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]), 0);
|
|
+#ifdef CONFIG_PPC
|
|
+ /* PPC requires a cacheable/non-coherent mapping of the portal */
|
|
+ va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]),
|
|
+ (pgprot_val(PAGE_KERNEL) & ~_PAGE_COHERENT));
|
|
+#else
|
|
+ /* For ARM we can use write combine mapping. */
|
|
+ va = ioremap_wc(addr_phys[0]->start, resource_size(addr_phys[0]));
|
|
+#endif
|
|
if (!va) {
|
|
dev_err(dev, "ioremap::CE failed\n");
|
|
goto err_ioremap1;
|
|
@@ -270,8 +277,7 @@ static int qman_portal_probe(struct plat
|
|
|
|
pcfg->addr_virt[DPAA_PORTAL_CE] = va;
|
|
|
|
- va = ioremap_prot(addr_phys[1]->start, resource_size(addr_phys[1]),
|
|
- _PAGE_GUARDED | _PAGE_NO_CACHE);
|
|
+ va = ioremap(addr_phys[1]->start, resource_size(addr_phys[1]));
|
|
if (!va) {
|
|
dev_err(dev, "ioremap::CI failed\n");
|
|
goto err_ioremap2;
|
|
--- a/drivers/soc/fsl/qbman/qman_priv.h
|
|
+++ b/drivers/soc/fsl/qbman/qman_priv.h
|
|
@@ -28,13 +28,13 @@
|
|
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
*/
|
|
|
|
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
|
|
-
|
|
#include "dpaa_sys.h"
|
|
|
|
#include <soc/fsl/qman.h>
|
|
#include <linux/dma-mapping.h>
|
|
#include <linux/iommu.h>
|
|
+#include <linux/dma-contiguous.h>
|
|
+#include <linux/of_address.h>
|
|
|
|
#if defined(CONFIG_FSL_PAMU)
|
|
#include <asm/fsl_pamu_stash.h>
|
|
@@ -187,6 +187,7 @@ struct qm_portal_config {
|
|
#define QMAN_REV20 0x0200
|
|
#define QMAN_REV30 0x0300
|
|
#define QMAN_REV31 0x0301
|
|
+#define QMAN_REV32 0x0302
|
|
extern u16 qman_ip_rev; /* 0 if uninitialised, otherwise QMAN_REVx */
|
|
|
|
#define QM_FQID_RANGE_START 1 /* FQID 0 reserved for internal use */
|
|
--- a/drivers/soc/fsl/qbman/qman_test.h
|
|
+++ b/drivers/soc/fsl/qbman/qman_test.h
|
|
@@ -30,7 +30,5 @@
|
|
|
|
#include "qman_priv.h"
|
|
|
|
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
|
|
-
|
|
int qman_test_stash(void);
|
|
int qman_test_api(void);
|