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3c1f6e358d
Patches are generated using the "format-patch" command from the following location: *https://www.codeaurora.org/cgit/quic/kernel/galak-msm/log/?h=apq_ipq_base *rev=0771849495b4128cac2faf7d49c85c729fc48b20 Patches numbered 76/77/102/103 have already been integrated in 3.14.12, so they're not in this list. All these patches are either integrated are pending integration into kernel.org, therefore these patches should go away once the kernel gets upgraded to 3.16. Support is currently limited to AP148 board but can be extended to other platforms in the future. These changes do not cover ethernet connectivity. Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> SVN-Revision: 42334
122 lines
3.0 KiB
Diff
122 lines
3.0 KiB
Diff
From b9b3815f2a71af88ca68d3524ee4d9b6b4739257 Mon Sep 17 00:00:00 2001
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From: Stephen Boyd <sboyd@codeaurora.org>
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Date: Wed, 18 Jun 2014 15:57:06 -0700
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Subject: [PATCH 174/182] clk: qcom: Add HFPLLs to IPQ806X driver
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Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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---
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drivers/clk/qcom/gcc-ipq806x.c | 83 ++++++++++++++++++++++++++++++++++++++++
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1 file changed, 83 insertions(+)
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diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
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index d80dc69..83a73cb 100644
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--- a/drivers/clk/qcom/gcc-ipq806x.c
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+++ b/drivers/clk/qcom/gcc-ipq806x.c
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@@ -30,6 +30,7 @@
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#include "clk-pll.h"
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#include "clk-rcg.h"
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#include "clk-branch.h"
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+#include "clk-hfpll.h"
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#include "reset.h"
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static struct clk_pll pll0 = {
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@@ -102,6 +103,85 @@ static struct clk_regmap pll8_vote = {
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},
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};
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+static struct hfpll_data hfpll0_data = {
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+ .mode_reg = 0x3200,
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+ .l_reg = 0x3208,
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+ .m_reg = 0x320c,
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+ .n_reg = 0x3210,
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+ .config_reg = 0x3204,
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+ .status_reg = 0x321c,
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+ .config_val = 0x7845c665,
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+ .droop_reg = 0x3214,
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+ .droop_val = 0x0108c000,
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+ .min_rate = 600000000UL,
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+ .max_rate = 1800000000UL,
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+};
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+
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+static struct clk_hfpll hfpll0 = {
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+ .d = &hfpll0_data,
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+ .clkr.hw.init = &(struct clk_init_data){
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+ .parent_names = (const char *[]){ "pxo" },
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+ .num_parents = 1,
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+ .name = "hfpll0",
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+ .ops = &clk_ops_hfpll,
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+ .flags = CLK_IGNORE_UNUSED,
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+ },
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+ .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
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+};
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+
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+static struct hfpll_data hfpll1_data = {
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+ .mode_reg = 0x3240,
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+ .l_reg = 0x3248,
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+ .m_reg = 0x324c,
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+ .n_reg = 0x3250,
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+ .config_reg = 0x3244,
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+ .status_reg = 0x325c,
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+ .config_val = 0x7845c665,
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+ .droop_reg = 0x3314,
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+ .droop_val = 0x0108c000,
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+ .min_rate = 600000000UL,
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+ .max_rate = 1800000000UL,
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+};
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+
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+static struct clk_hfpll hfpll1 = {
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+ .d = &hfpll1_data,
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+ .clkr.hw.init = &(struct clk_init_data){
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+ .parent_names = (const char *[]){ "pxo" },
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+ .num_parents = 1,
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+ .name = "hfpll1",
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+ .ops = &clk_ops_hfpll,
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+ .flags = CLK_IGNORE_UNUSED,
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+ },
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+ .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
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+};
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+
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+static struct hfpll_data hfpll_l2_data = {
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+ .mode_reg = 0x3300,
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+ .l_reg = 0x3308,
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+ .m_reg = 0x330c,
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+ .n_reg = 0x3310,
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+ .config_reg = 0x3304,
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+ .status_reg = 0x331c,
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+ .config_val = 0x7845c665,
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+ .droop_reg = 0x3314,
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+ .droop_val = 0x0108c000,
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+ .min_rate = 600000000UL,
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+ .max_rate = 1800000000UL,
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+};
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+
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+static struct clk_hfpll hfpll_l2 = {
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+ .d = &hfpll_l2_data,
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+ .clkr.hw.init = &(struct clk_init_data){
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+ .parent_names = (const char *[]){ "pxo" },
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+ .num_parents = 1,
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+ .name = "hfpll_l2",
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+ .ops = &clk_ops_hfpll,
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+ .flags = CLK_IGNORE_UNUSED,
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+ },
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+ .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
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+};
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+
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+
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static struct clk_pll pll14 = {
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.l_reg = 0x31c4,
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.m_reg = 0x31c8,
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@@ -2878,6 +2958,9 @@ static struct clk_regmap *gcc_ipq806x_clks[] = {
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[NSSTCM_CLK_SRC] = &nss_tcm_src.clkr,
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[NSSTCM_CLK] = &nss_tcm_clk.clkr,
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[NSS_CORE_CLK] = &nss_core_clk,
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+ [PLL9] = &hfpll0.clkr,
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+ [PLL10] = &hfpll1.clkr,
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+ [PLL12] = &hfpll_l2.clkr,
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};
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static const struct qcom_reset_map gcc_ipq806x_resets[] = {
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--
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1.7.10.4
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