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188 lines
5.0 KiB
Diff
188 lines
5.0 KiB
Diff
From 6d3ca59232090bff1b5e1abfd3417a3859e47425 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
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Date: Mon, 23 Dec 2013 00:32:38 -0300
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Subject: [PATCH] ARM: sunxi: add PLL5 and PLL6 support
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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This commit adds PLL5 and PLL6 nodes to the sun4i, sun5i and sun7i
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device trees.
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Signed-off-by: Emilio López <emilio@elopez.com.ar>
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Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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arch/arm/boot/dts/sun4i-a10.dtsi | 19 +++++++++++++++++--
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arch/arm/boot/dts/sun5i-a10s.dtsi | 19 +++++++++++++++++--
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arch/arm/boot/dts/sun5i-a13.dtsi | 19 +++++++++++++++++--
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arch/arm/boot/dts/sun7i-a20.dtsi | 28 ++++++++++++++++------------
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4 files changed, 67 insertions(+), 18 deletions(-)
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--- a/arch/arm/boot/dts/sun4i-a10.dtsi
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+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
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@@ -73,6 +73,22 @@
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clocks = <&osc24M>;
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};
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+ pll5: pll5@01c20020 {
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+ #clock-cells = <1>;
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+ compatible = "allwinner,sun4i-pll5-clk";
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+ reg = <0x01c20020 0x4>;
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+ clocks = <&osc24M>;
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+ clock-output-names = "pll5_ddr", "pll5_other";
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+ };
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+
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+ pll6: pll6@01c20028 {
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+ #clock-cells = <1>;
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+ compatible = "allwinner,sun4i-pll6-clk";
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+ reg = <0x01c20028 0x4>;
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+ clocks = <&osc24M>;
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+ clock-output-names = "pll6_sata", "pll6_other", "pll6";
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+ };
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+
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/* dummy is 200M */
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cpu: cpu@01c20054 {
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#clock-cells = <0>;
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@@ -138,12 +154,11 @@
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"apb0_ir1", "apb0_keypad";
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};
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- /* dummy is pll62 */
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apb1_mux: apb1_mux@01c20058 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-apb1-mux-clk";
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reg = <0x01c20058 0x4>;
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- clocks = <&osc24M>, <&dummy>, <&osc32k>;
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+ clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
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};
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apb1: apb1@01c20058 {
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--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
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+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
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@@ -70,6 +70,22 @@
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clocks = <&osc24M>;
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};
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+ pll5: pll5@01c20020 {
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+ #clock-cells = <1>;
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+ compatible = "allwinner,sun4i-pll5-clk";
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+ reg = <0x01c20020 0x4>;
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+ clocks = <&osc24M>;
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+ clock-output-names = "pll5_ddr", "pll5_other";
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+ };
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+
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+ pll6: pll6@01c20028 {
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+ #clock-cells = <1>;
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+ compatible = "allwinner,sun4i-pll6-clk";
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+ reg = <0x01c20028 0x4>;
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+ clocks = <&osc24M>;
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+ clock-output-names = "pll6_sata", "pll6_other", "pll6";
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+ };
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+
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/* dummy is 200M */
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cpu: cpu@01c20054 {
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#clock-cells = <0>;
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@@ -130,12 +146,11 @@
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"apb0_ir", "apb0_keypad";
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};
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- /* dummy is pll62 */
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apb1_mux: apb1_mux@01c20058 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-apb1-mux-clk";
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reg = <0x01c20058 0x4>;
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- clocks = <&osc24M>, <&dummy>, <&osc32k>;
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+ clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
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};
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apb1: apb1@01c20058 {
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--- a/arch/arm/boot/dts/sun5i-a13.dtsi
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+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
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@@ -74,6 +74,22 @@
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clocks = <&osc24M>;
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};
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+ pll5: pll5@01c20020 {
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+ #clock-cells = <1>;
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+ compatible = "allwinner,sun4i-pll5-clk";
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+ reg = <0x01c20020 0x4>;
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+ clocks = <&osc24M>;
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+ clock-output-names = "pll5_ddr", "pll5_other";
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+ };
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+
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+ pll6: pll6@01c20028 {
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+ #clock-cells = <1>;
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+ compatible = "allwinner,sun4i-pll6-clk";
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+ reg = <0x01c20028 0x4>;
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+ clocks = <&osc24M>;
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+ clock-output-names = "pll6_sata", "pll6_other", "pll6";
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+ };
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+
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/* dummy is 200M */
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cpu: cpu@01c20054 {
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#clock-cells = <0>;
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@@ -132,12 +148,11 @@
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clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
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};
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- /* dummy is pll6 */
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apb1_mux: apb1_mux@01c20058 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-apb1-mux-clk";
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reg = <0x01c20058 0x4>;
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- clocks = <&osc24M>, <&dummy>, <&osc32k>;
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+ clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
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};
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apb1: apb1@01c20058 {
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--- a/arch/arm/boot/dts/sun7i-a20.dtsi
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+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
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@@ -69,23 +69,27 @@
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clocks = <&osc24M>;
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};
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- /*
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- * This is a dummy clock, to be used as placeholder on
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- * other mux clocks when a specific parent clock is not
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- * yet implemented. It should be dropped when the driver
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- * is complete.
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- */
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- pll6: pll6 {
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- #clock-cells = <0>;
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- compatible = "fixed-clock";
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- clock-frequency = <0>;
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+ pll5: pll5@01c20020 {
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+ #clock-cells = <1>;
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+ compatible = "allwinner,sun4i-pll5-clk";
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+ reg = <0x01c20020 0x4>;
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+ clocks = <&osc24M>;
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+ clock-output-names = "pll5_ddr", "pll5_other";
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+ };
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+
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+ pll6: pll6@01c20028 {
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+ #clock-cells = <1>;
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+ compatible = "allwinner,sun4i-pll6-clk";
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+ reg = <0x01c20028 0x4>;
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+ clocks = <&osc24M>;
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+ clock-output-names = "pll6_sata", "pll6_other", "pll6";
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};
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cpu: cpu@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-cpu-clk";
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reg = <0x01c20054 0x4>;
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- clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>;
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+ clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
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};
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axi: axi@01c20054 {
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@@ -144,7 +148,7 @@
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-apb1-mux-clk";
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reg = <0x01c20058 0x4>;
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- clocks = <&osc24M>, <&pll6>, <&osc32k>;
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+ clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
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};
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apb1: apb1@01c20058 {
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