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99 lines
2.9 KiB
Diff
99 lines
2.9 KiB
Diff
From 5b837e6c8499aa9bdf9f76889247feac553870d0 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jonas.gorski@gmail.com>
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Date: Sun, 28 Oct 2012 13:09:38 +0100
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Subject: [PATCH 3/3] MIPS: BCM63XX: use the new reset helper
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Use the new reset helper where appropriate.
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Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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---
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arch/mips/bcm63xx/clk.c | 19 +++++--------------
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arch/mips/pci/pci-bcm63xx.c | 19 ++++++-------------
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2 files changed, 11 insertions(+), 27 deletions(-)
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--- a/arch/mips/bcm63xx/clk.c
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+++ b/arch/mips/bcm63xx/clk.c
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@@ -14,6 +14,7 @@
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#include <bcm63xx_cpu.h>
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#include <bcm63xx_io.h>
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#include <bcm63xx_regs.h>
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+#include <bcm63xx_reset.h>
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#include <bcm63xx_clk.h>
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static DEFINE_MUTEX(clocks_mutex);
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@@ -124,15 +125,10 @@ static void enetsw_set(struct clk *clk,
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CKCTL_6368_SWPKT_USB_EN |
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CKCTL_6368_SWPKT_SAR_EN, enable);
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if (enable) {
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- u32 val;
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-
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/* reset switch core afer clock change */
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- val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
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- val &= ~SOFTRESET_6368_ENETSW_MASK;
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- bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
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+ bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 1);
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msleep(10);
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- val |= SOFTRESET_6368_ENETSW_MASK;
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- bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
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+ bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 0);
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msleep(10);
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}
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}
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@@ -222,15 +218,10 @@ static void xtm_set(struct clk *clk, int
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CKCTL_6368_SWPKT_SAR_EN, enable);
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if (enable) {
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- u32 val;
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-
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/* reset sar core afer clock change */
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- val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
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- val &= ~SOFTRESET_6368_SAR_MASK;
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- bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
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+ bcm63xx_core_set_reset(BCM63XX_RESET_SAR, 1);
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mdelay(1);
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- val |= SOFTRESET_6368_SAR_MASK;
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- bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
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+ bcm63xx_core_set_reset(BCM63XX_RESET_SAR, 0);
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mdelay(1);
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}
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}
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--- a/arch/mips/pci/pci-bcm63xx.c
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+++ b/arch/mips/pci/pci-bcm63xx.c
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@@ -13,6 +13,8 @@
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#include <linux/delay.h>
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#include <asm/bootinfo.h>
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+#include <bcm63xx_reset.h>
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+
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#include "pci-bcm63xx.h"
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/*
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@@ -130,23 +132,14 @@ static void __init bcm63xx_reset_pcie(vo
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bcm_misc_writel(val, MISC_SERDES_CTRL_REG);
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/* reset the PCIe core */
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- val = bcm_perf_readl(PERF_SOFTRESET_6328_REG);
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-
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- val &= ~SOFTRESET_6328_PCIE_MASK;
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- val &= ~SOFTRESET_6328_PCIE_CORE_MASK;
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- val &= ~SOFTRESET_6328_PCIE_HARD_MASK;
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- val &= ~SOFTRESET_6328_PCIE_EXT_MASK;
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- bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
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+ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1);
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+ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 1);
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mdelay(10);
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- val |= SOFTRESET_6328_PCIE_MASK;
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- val |= SOFTRESET_6328_PCIE_CORE_MASK;
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- val |= SOFTRESET_6328_PCIE_HARD_MASK;
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- bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
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+ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 0);
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mdelay(10);
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- val |= SOFTRESET_6328_PCIE_EXT_MASK;
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- bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
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+ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 0);
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mdelay(200);
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}
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