mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-22 06:57:57 +00:00
33e72e0b3d
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.1.79 Manually rebased: ath79/patches-6.1/900-unaligned_access_hacks.patch All other patches automatically rebased. Build system: x86/64 Build-tested: x86/64/AMD Cezanne, ramips/tplink_archer-a6-v3, flogic/xiaomi_redmi-router-ax6000-ubootmod Run-tested: x86/64/AMD Cezanne, ramips/tplink_archer-a6-v3, flogic/xiaomi_redmi-router-ax6000-ubootmod Signed-off-by: John Audia <therealgraysky@proton.me>
74 lines
2.7 KiB
Diff
74 lines
2.7 KiB
Diff
From fa4d4ed28c92cf4470e518f1a7362dc7941632d7 Mon Sep 17 00:00:00 2001
|
|
From: Dom Cobley <popcornmix@gmail.com>
|
|
Date: Wed, 28 Jun 2023 16:24:29 +0100
|
|
Subject: [PATCH] irqchip/irq-brcmstb-l2: Add config for 2711 controller
|
|
|
|
We currently see these regularly:
|
|
[ 25.157560] irq 31, desc: 00000000c15e6d2c, depth: 0, count: 0, unhandled: 0
|
|
[ 25.164658] ->handle_irq(): 00000000b1775675, brcmstb_l2_intc_irq_handle+0x0/0x1a8
|
|
[ 25.172352] ->irq_data.chip(): 00000000fea59f1c, gic_chip_mode1+0x0/0x108
|
|
[ 25.179166] ->action(): 000000003eda6d6f
|
|
[ 25.183096] ->action->handler(): 000000002c09e646, bad_chained_irq+0x0/0x58
|
|
[ 25.190084] IRQ_LEVEL set
|
|
[ 25.193142] IRQ_NOPROBE set
|
|
[ 25.196198] IRQ_NOREQUEST set
|
|
[ 25.199255] IRQ_NOTHREAD set
|
|
|
|
with:
|
|
$ cat /proc/interrupts | grep 31:
|
|
31: 1 0 0 0 GICv2 129 Level (null)
|
|
|
|
The interrupt is described in DT with IRQ_TYPE_LEVEL_HIGH
|
|
|
|
But the current compatible string uses the controller in edge triggered mode
|
|
(as that config matches our register layout).
|
|
|
|
Add a new compatible structure for level driven interrupt with our register layout.
|
|
|
|
We had already been using this compatible string in device tree, so no change needed
|
|
there.
|
|
|
|
Signed-off-by: Dom Cobley <popcornmix@gmail.com>
|
|
---
|
|
drivers/irqchip/irq-brcmstb-l2.c | 17 +++++++++++++++++
|
|
1 file changed, 17 insertions(+)
|
|
|
|
--- a/drivers/irqchip/irq-brcmstb-l2.c
|
|
+++ b/drivers/irqchip/irq-brcmstb-l2.c
|
|
@@ -52,6 +52,16 @@ static const struct brcmstb_intc_init_pa
|
|
.cpu_mask_clear = 0x0C
|
|
};
|
|
|
|
+/* Register offsets in the 2711 L2 level interrupt controller */
|
|
+static const struct brcmstb_intc_init_params l2_2711_lvl_intc_init = {
|
|
+ .handler = handle_level_irq,
|
|
+ .cpu_status = 0x00,
|
|
+ .cpu_clear = 0x08,
|
|
+ .cpu_mask_status = 0x0c,
|
|
+ .cpu_mask_set = 0x10,
|
|
+ .cpu_mask_clear = 0x14
|
|
+};
|
|
+
|
|
/* L2 intc private data structure */
|
|
struct brcmstb_l2_intc_data {
|
|
struct irq_domain *domain;
|
|
@@ -289,11 +299,18 @@ static int __init brcmstb_l2_lvl_intc_of
|
|
return brcmstb_l2_intc_of_init(np, parent, &l2_lvl_intc_init);
|
|
}
|
|
|
|
+static int __init brcmstb_l2_2711_lvl_intc_of_init(struct device_node *np,
|
|
+ struct device_node *parent)
|
|
+{
|
|
+ return brcmstb_l2_intc_of_init(np, parent, &l2_2711_lvl_intc_init);
|
|
+}
|
|
+
|
|
IRQCHIP_PLATFORM_DRIVER_BEGIN(brcmstb_l2)
|
|
IRQCHIP_MATCH("brcm,l2-intc", brcmstb_l2_edge_intc_of_init)
|
|
IRQCHIP_MATCH("brcm,hif-spi-l2-intc", brcmstb_l2_edge_intc_of_init)
|
|
IRQCHIP_MATCH("brcm,upg-aux-aon-l2-intc", brcmstb_l2_edge_intc_of_init)
|
|
IRQCHIP_MATCH("brcm,bcm7271-l2-intc", brcmstb_l2_lvl_intc_of_init)
|
|
+IRQCHIP_MATCH("brcm,bcm2711-l2-intc", brcmstb_l2_2711_lvl_intc_of_init)
|
|
IRQCHIP_PLATFORM_DRIVER_END(brcmstb_l2)
|
|
MODULE_DESCRIPTION("Broadcom STB generic L2 interrupt controller");
|
|
MODULE_LICENSE("GPL v2");
|