mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-23 15:32:33 +00:00
6f398aa762
Reboot the oxnas target based on Linux 4.14 by rebasing our support on top of the now-existing upstream kernel support. This commit brings oxnas support to the level of v4.17 having upstream drivers for Ethernet, Serial and NAND flash. Botch up OpenWrt's local drivers for EHCI, SATA and PCIe based on the new platform code and device-tree. Re-introduce base-files from old oxnas target which works for now but needs further clean-up towards generic board support. Functional issues: * PCIe won't come up (hence no USB3 on Shuttle KD20) * I2C bus of Akitio myCloud device is likely not to work (missing debounce support in new pinctrl driver) Code-style issues: * plla/pllb needs further cleanup -- currently their users are writing into the syscon regmap after acquireling the clk instead of using defined clk_*_*() functions to setup multipliers and dividors. * PCIe phy needs its own little driver. * SATA driver is a monster and should be split into an mfd having a raidctrl regmap, sata controller, sata ports and sata phy. Tested on MitraStar STG-212 aka. Medion Akoya MD86xxx and Shuttle KD20. Signed-off-by: Daniel Golle <daniel@makrotopia.org> (squash-picked commit17511a7ea8and commitdcc34574effrom master)
71 lines
2.0 KiB
Diff
71 lines
2.0 KiB
Diff
From 552ed4955c1fee1109bf5ba137dc35a411a1448c Mon Sep 17 00:00:00 2001
|
|
From: Daniel Golle <daniel@makrotopia.org>
|
|
Date: Fri, 1 Jun 2018 02:41:15 +0200
|
|
Subject: [PATCH] arm: ox820: remove left-overs
|
|
|
|
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
|
---
|
|
drivers/clk/clk-oxnas.c | 2 --
|
|
include/dt-bindings/clock/oxsemi,ox820.h | 32 +++++++++++-------------
|
|
2 files changed, 14 insertions(+), 20 deletions(-)
|
|
|
|
diff --git a/drivers/clk/clk-oxnas.c b/drivers/clk/clk-oxnas.c
|
|
index e51e0023fc6e..da6af71649de 100644
|
|
--- a/drivers/clk/clk-oxnas.c
|
|
+++ b/drivers/clk/clk-oxnas.c
|
|
@@ -40,8 +40,6 @@ struct oxnas_stdclk_data {
|
|
struct clk_hw_onecell_data *onecell_data;
|
|
struct clk_oxnas_gate **gates;
|
|
unsigned int ngates;
|
|
- struct clk_oxnas_pll **plls;
|
|
- unsigned int nplls;
|
|
};
|
|
|
|
/* Regmap offsets */
|
|
diff --git a/include/dt-bindings/clock/oxsemi,ox820.h b/include/dt-bindings/clock/oxsemi,ox820.h
|
|
index f661ecc8d760..35b44ca1b104 100644
|
|
--- a/include/dt-bindings/clock/oxsemi,ox820.h
|
|
+++ b/include/dt-bindings/clock/oxsemi,ox820.h
|
|
@@ -17,24 +17,20 @@
|
|
#ifndef DT_CLOCK_OXSEMI_OX820_H
|
|
#define DT_CLOCK_OXSEMI_OX820_H
|
|
|
|
-/* PLLs */
|
|
-#define CLK_820_PLLA 0
|
|
-#define CLK_820_PLLB 1
|
|
-
|
|
/* Gate Clocks */
|
|
-#define CLK_820_LEON 2
|
|
-#define CLK_820_DMA_SGDMA 3
|
|
-#define CLK_820_CIPHER 4
|
|
-#define CLK_820_SD 5
|
|
-#define CLK_820_SATA 6
|
|
-#define CLK_820_AUDIO 7
|
|
-#define CLK_820_USBMPH 8
|
|
-#define CLK_820_ETHA 9
|
|
-#define CLK_820_PCIEA 10
|
|
-#define CLK_820_NAND 11
|
|
-#define CLK_820_PCIEB 12
|
|
-#define CLK_820_ETHB 13
|
|
-#define CLK_820_REF600 14
|
|
-#define CLK_820_USBDEV 15
|
|
+#define CLK_820_LEON 0
|
|
+#define CLK_820_DMA_SGDMA 1
|
|
+#define CLK_820_CIPHER 2
|
|
+#define CLK_820_SD 3
|
|
+#define CLK_820_SATA 4
|
|
+#define CLK_820_AUDIO 5
|
|
+#define CLK_820_USBMPH 6
|
|
+#define CLK_820_ETHA 7
|
|
+#define CLK_820_PCIEA 8
|
|
+#define CLK_820_NAND 9
|
|
+#define CLK_820_PCIEB 10
|
|
+#define CLK_820_ETHB 11
|
|
+#define CLK_820_REF600 12
|
|
+#define CLK_820_USBDEV 13
|
|
|
|
#endif /* DT_CLOCK_OXSEMI_OX820_H */
|
|
--
|
|
2.17.1
|
|
|