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e4ce3109f2
The node pinctrl0 is already set up in the SOC DTSI files, but defined again as member of pinctrl in most of the device DTS(I) files. This patch removes this redundancy for the entire ramips target. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
191 lines
2.9 KiB
Plaintext
191 lines
2.9 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "mt7620a.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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compatible = "ralink,mt7620a-soc";
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aliases {
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led-boot = &led_power;
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led-failsafe = &led_power;
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led-running = &led_power;
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led-upgrade = &led_power;
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};
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chosen {
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bootargs = "console=ttyS0,57600";
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};
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keys {
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compatible = "gpio-keys";
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reset_wps {
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label = "reset_wps";
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gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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switch_high {
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label = "switch high";
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gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
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linux,code = <BTN_0>;
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linux,input-type = <EV_SW>;
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};
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switch_off {
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label = "switch off";
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gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
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linux,code = <BTN_1>;
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linux,input-type = <EV_SW>;
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};
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};
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};
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&gpio1 {
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status = "okay";
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};
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&gpio2 {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x30000>;
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read-only;
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};
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partition@30000 {
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label = "u-boot-env";
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reg = <0x30000 0x10000>;
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read-only;
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};
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factory: partition@40000 {
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label = "factory";
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reg = <0x40000 0x10000>;
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read-only;
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};
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partition@50000 {
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label = "cimage";
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reg = <0x50000 0x20000>;
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read-only;
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};
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partition@70000 {
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compatible = "edimax,uimage";
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label = "firmware";
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reg = <0x00070000 0x00790000>;
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};
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};
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};
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};
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&state_default {
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gpio {
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ralink,group = "i2c", "uartf", "nd_sd", "rgmii2";
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ralink,function = "gpio";
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};
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};
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&pinctrl {
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phy_reset_pins: phy-reset {
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gpio {
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ralink,group = "spi refclk";
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ralink,function = "gpio";
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};
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};
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};
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ðernet {
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status = "okay";
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mtd-mac-address = <&factory 0x4>;
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii1_pins &mdio_pins &phy_reset_pins>;
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mediatek,portmap = "l";
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mediatek,mdio-mode = <1>;
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phy-reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <30>;
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port@5 {
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status = "okay";
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mediatek,fixed-link = <1000 1 1 1>;
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phy-mode = "rgmii";
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};
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mdio-bus {
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status = "okay";
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phy0: ethernet-phy@0 {
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status = "disabled";
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reg = <0>;
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phy-mode = "rgmii";
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};
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phy1: ethernet-phy@1 {
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status = "disabled";
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reg = <1>;
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phy-mode = "rgmii";
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};
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phy2: ethernet-phy@2 {
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status = "disabled";
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reg = <2>;
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phy-mode = "rgmii";
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};
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phy3: ethernet-phy@3 {
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status = "disabled";
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reg = <3>;
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phy-mode = "rgmii";
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};
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phy4: ethernet-phy@4 {
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status = "disabled";
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reg = <4>;
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phy-mode = "rgmii";
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};
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};
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};
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&gsw {
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mediatek,port5 = "gmac";
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};
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&wmac {
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ralink,mtd-eeprom = <&factory 0>;
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};
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&pcie {
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status = "okay";
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};
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&pcie0 {
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wifi@0,0 {
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reg = <0x0000 0 0 0 0>;
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mediatek,mtd-eeprom = <&factory 0x8000>;
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mediatek,2ghz = <0>;
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};
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};
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