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f2f42a54e8
The qca8k patch series brings the numbering to 799. This patch renames 7xx patches to create space for more backports to be added. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> [rename 729->719] Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
189 lines
6.6 KiB
Diff
189 lines
6.6 KiB
Diff
From e4b9977cee1583da38a6e9118078bb728aaccf7b Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Fri, 14 May 2021 23:00:06 +0200
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Subject: [PATCH] net: dsa: qca8k: make rgmii delay configurable
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The legacy qsdk code used a different delay instead of the max value.
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Qsdk use 1 ns for rx and 2 ns for tx. Make these values configurable
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using the standard rx/tx-internal-delay-ps ethernet binding and apply
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qsdk values by default. The connected gmac doesn't add any delay so no
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additional delay is added to tx/rx.
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On this switch the delay is actually in ns so value should be in the
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1000 order. Any value converted from ps to ns by dividing it by 1000
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as the switch max value for delay is 3ns.
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/dsa/qca8k.c | 82 ++++++++++++++++++++++++++++++++++++++++-
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drivers/net/dsa/qca8k.h | 11 +++---
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2 files changed, 86 insertions(+), 7 deletions(-)
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--- a/drivers/net/dsa/qca8k.c
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+++ b/drivers/net/dsa/qca8k.c
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@@ -778,6 +778,68 @@ qca8k_setup_mdio_bus(struct qca8k_priv *
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}
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static int
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+qca8k_setup_of_rgmii_delay(struct qca8k_priv *priv)
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+{
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+ struct device_node *port_dn;
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+ phy_interface_t mode;
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+ struct dsa_port *dp;
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+ u32 val;
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+
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+ /* CPU port is already checked */
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+ dp = dsa_to_port(priv->ds, 0);
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+
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+ port_dn = dp->dn;
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+
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+ /* Check if port 0 is set to the correct type */
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+ of_get_phy_mode(port_dn, &mode);
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+ if (mode != PHY_INTERFACE_MODE_RGMII_ID &&
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+ mode != PHY_INTERFACE_MODE_RGMII_RXID &&
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+ mode != PHY_INTERFACE_MODE_RGMII_TXID) {
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+ return 0;
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+ }
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+
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+ switch (mode) {
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+ case PHY_INTERFACE_MODE_RGMII_ID:
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+ case PHY_INTERFACE_MODE_RGMII_RXID:
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+ if (of_property_read_u32(port_dn, "rx-internal-delay-ps", &val))
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+ val = 2;
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+ else
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+ /* Switch regs accept value in ns, convert ps to ns */
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+ val = val / 1000;
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+
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+ if (val > QCA8K_MAX_DELAY) {
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+ dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value");
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+ val = 3;
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+ }
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+
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+ priv->rgmii_rx_delay = val;
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+ /* Stop here if we need to check only for rx delay */
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+ if (mode != PHY_INTERFACE_MODE_RGMII_ID)
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+ break;
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+
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+ fallthrough;
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+ case PHY_INTERFACE_MODE_RGMII_TXID:
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+ if (of_property_read_u32(port_dn, "tx-internal-delay-ps", &val))
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+ val = 1;
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+ else
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+ /* Switch regs accept value in ns, convert ps to ns */
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+ val = val / 1000;
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+
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+ if (val > QCA8K_MAX_DELAY) {
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+ dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value");
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+ val = 3;
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+ }
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+
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+ priv->rgmii_tx_delay = val;
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+ break;
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+ default:
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+ return 0;
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+ }
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+
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+ return 0;
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+}
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+
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+static int
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qca8k_setup(struct dsa_switch *ds)
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{
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struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
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@@ -802,6 +864,10 @@ qca8k_setup(struct dsa_switch *ds)
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if (ret)
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return ret;
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+ ret = qca8k_setup_of_rgmii_delay(priv);
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+ if (ret)
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+ return ret;
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+
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/* Enable CPU Port */
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ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
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QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
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@@ -970,6 +1036,8 @@ qca8k_phylink_mac_config(struct dsa_swit
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case 0: /* 1st CPU port */
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if (state->interface != PHY_INTERFACE_MODE_RGMII &&
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state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
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+ state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
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+ state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
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state->interface != PHY_INTERFACE_MODE_SGMII)
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return;
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@@ -985,6 +1053,8 @@ qca8k_phylink_mac_config(struct dsa_swit
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case 6: /* 2nd CPU port / external PHY */
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if (state->interface != PHY_INTERFACE_MODE_RGMII &&
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state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
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+ state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
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+ state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
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state->interface != PHY_INTERFACE_MODE_SGMII &&
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state->interface != PHY_INTERFACE_MODE_1000BASEX)
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return;
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@@ -1008,14 +1078,18 @@ qca8k_phylink_mac_config(struct dsa_swit
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qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN);
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break;
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case PHY_INTERFACE_MODE_RGMII_ID:
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+ case PHY_INTERFACE_MODE_RGMII_TXID:
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+ case PHY_INTERFACE_MODE_RGMII_RXID:
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/* RGMII_ID needs internal delay. This is enabled through
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* PORT5_PAD_CTRL for all ports, rather than individual port
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* registers
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*/
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qca8k_write(priv, reg,
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QCA8K_PORT_PAD_RGMII_EN |
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- QCA8K_PORT_PAD_RGMII_TX_DELAY(QCA8K_MAX_DELAY) |
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- QCA8K_PORT_PAD_RGMII_RX_DELAY(QCA8K_MAX_DELAY));
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+ QCA8K_PORT_PAD_RGMII_TX_DELAY(priv->rgmii_tx_delay) |
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+ QCA8K_PORT_PAD_RGMII_RX_DELAY(priv->rgmii_rx_delay) |
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+ QCA8K_PORT_PAD_RGMII_TX_DELAY_EN |
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+ QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
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/* QCA8337 requires to set rgmii rx delay */
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if (priv->switch_id == QCA8K_ID_QCA8337)
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qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
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@@ -1073,6 +1147,8 @@ qca8k_phylink_validate(struct dsa_switch
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if (state->interface != PHY_INTERFACE_MODE_NA &&
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state->interface != PHY_INTERFACE_MODE_RGMII &&
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state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
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+ state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
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+ state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
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state->interface != PHY_INTERFACE_MODE_SGMII)
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goto unsupported;
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break;
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@@ -1090,6 +1166,8 @@ qca8k_phylink_validate(struct dsa_switch
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if (state->interface != PHY_INTERFACE_MODE_NA &&
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state->interface != PHY_INTERFACE_MODE_RGMII &&
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state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
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+ state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
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+ state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
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state->interface != PHY_INTERFACE_MODE_SGMII &&
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state->interface != PHY_INTERFACE_MODE_1000BASEX)
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goto unsupported;
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--- a/drivers/net/dsa/qca8k.h
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+++ b/drivers/net/dsa/qca8k.h
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@@ -38,12 +38,11 @@
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#define QCA8K_REG_PORT5_PAD_CTRL 0x008
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#define QCA8K_REG_PORT6_PAD_CTRL 0x00c
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#define QCA8K_PORT_PAD_RGMII_EN BIT(26)
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-#define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) \
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- ((0x8 + (x & 0x3)) << 22)
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-#define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) \
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- ((0x10 + (x & 0x3)) << 20)
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-#define QCA8K_MAX_DELAY 3
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+#define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) ((x) << 22)
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+#define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) ((x) << 20)
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+#define QCA8K_PORT_PAD_RGMII_TX_DELAY_EN BIT(25)
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#define QCA8K_PORT_PAD_RGMII_RX_DELAY_EN BIT(24)
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+#define QCA8K_MAX_DELAY 3
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#define QCA8K_PORT_PAD_SGMII_EN BIT(7)
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#define QCA8K_REG_PWS 0x010
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#define QCA8K_PWS_SERDES_AEN_DIS BIT(7)
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@@ -254,6 +253,8 @@ struct qca8k_match_data {
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struct qca8k_priv {
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u8 switch_id;
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u8 switch_revision;
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+ u8 rgmii_tx_delay;
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+ u8 rgmii_rx_delay;
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struct regmap *regmap;
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struct mii_bus *bus;
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struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS];
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