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8e5de89769
Manually adapted: layerscape/patches-5.4/820-usb-0009-usb-dwc3-Add-workaround-for-host-mode-VBUS-glitch-wh.patch Compile-tested: x86/64 Run-tested: x86/64 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
43 lines
1.5 KiB
Diff
43 lines
1.5 KiB
Diff
From a9f1d7994a9f8a38fdace19454ef031244e24e5e Mon Sep 17 00:00:00 2001
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From: Peter Chen <peter.chen@nxp.com>
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Date: Thu, 9 Nov 2017 16:58:40 +0800
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Subject: [PATCH] MLK-16735 usb: host: add XHCI_CDNS_HOST flag
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The NXP Cadence XHCI host has the same issue with Intel's,
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it is triggered by reboot test, the test case is described
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at this jira ticket.
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BuildInfo:
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- SCFW 8dcff26, IMX-MKIMAGE ea027c4b, ATF
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- U-Boot 2017.03-imx_v2017.03_4.9.51_imx8_beta1+g6dc7b0f
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Acked-by: Jun Li <jun.li@nxp.com>
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Signed-off-by: Peter Chen <peter.chen@nxp.com>
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(cherry picked from commit 5e353132931b9dc6e05f6bea1281ae35dd6a59d8)
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---
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drivers/usb/host/xhci.c | 2 +-
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drivers/usb/host/xhci.h | 1 +
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2 files changed, 2 insertions(+), 1 deletion(-)
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--- a/drivers/usb/host/xhci.c
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+++ b/drivers/usb/host/xhci.c
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@@ -195,7 +195,7 @@ int xhci_reset(struct xhci_hcd *xhci, u6
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* Without this delay, the subsequent HC register access,
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* may result in a system hang very rarely.
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*/
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- if (xhci->quirks & XHCI_INTEL_HOST)
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+ if (xhci->quirks & (XHCI_INTEL_HOST | XHCI_CDNS_HOST))
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udelay(1000);
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ret = xhci_handshake(&xhci->op_regs->command, CMD_RESET, 0, timeout_us);
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--- a/drivers/usb/host/xhci.h
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+++ b/drivers/usb/host/xhci.h
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@@ -1880,6 +1880,7 @@ struct xhci_hcd {
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#define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33)
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#define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34)
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#define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
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+#define XHCI_CDNS_HOST BIT_ULL(36)
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#define XHCI_SKIP_PHY_INIT BIT_ULL(37)
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#define XHCI_DISABLE_SPARSE BIT_ULL(38)
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#define XHCI_NO_SOFT_RETRY BIT_ULL(40)
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