mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-25 16:31:13 +00:00
46468fc9d5
Replace recently added patches with version accepted upstream. Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
87 lines
2.6 KiB
Diff
87 lines
2.6 KiB
Diff
From 49293bbc50cb7d44223eb49e0f7cb38e7dac2361 Mon Sep 17 00:00:00 2001
|
|
From: Aleksander Jan Bajkowski <olek2@wp.pl>
|
|
Date: Tue, 14 Sep 2021 23:21:01 +0200
|
|
Subject: [PATCH 4/5] MIPS: lantiq: dma: make the burst length configurable by
|
|
the drivers
|
|
|
|
Make the burst length configurable by the drivers.
|
|
|
|
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
|
|
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
|
|
Signed-off-by: David S. Miller <davem@davemloft.net>
|
|
---
|
|
.../include/asm/mach-lantiq/xway/xway_dma.h | 2 +-
|
|
arch/mips/lantiq/xway/dma.c | 38 ++++++++++++++++---
|
|
2 files changed, 34 insertions(+), 6 deletions(-)
|
|
|
|
--- a/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
|
|
+++ b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
|
|
@@ -45,6 +45,6 @@ extern void ltq_dma_close(struct ltq_dma
|
|
extern void ltq_dma_alloc_tx(struct ltq_dma_channel *ch);
|
|
extern void ltq_dma_alloc_rx(struct ltq_dma_channel *ch);
|
|
extern void ltq_dma_free(struct ltq_dma_channel *ch);
|
|
-extern void ltq_dma_init_port(int p);
|
|
+extern void ltq_dma_init_port(int p, int tx_burst, int rx_burst);
|
|
|
|
#endif
|
|
--- a/arch/mips/lantiq/xway/dma.c
|
|
+++ b/arch/mips/lantiq/xway/dma.c
|
|
@@ -181,7 +181,7 @@ ltq_dma_free(struct ltq_dma_channel *ch)
|
|
EXPORT_SYMBOL_GPL(ltq_dma_free);
|
|
|
|
void
|
|
-ltq_dma_init_port(int p)
|
|
+ltq_dma_init_port(int p, int tx_burst, int rx_burst)
|
|
{
|
|
ltq_dma_w32(p, LTQ_DMA_PS);
|
|
switch (p) {
|
|
@@ -190,16 +190,44 @@ ltq_dma_init_port(int p)
|
|
* Tell the DMA engine to swap the endianness of data frames and
|
|
* drop packets if the channel arbitration fails.
|
|
*/
|
|
- ltq_dma_w32_mask(0, DMA_ETOP_ENDIANNESS | DMA_PDEN,
|
|
+ ltq_dma_w32_mask(0, (DMA_ETOP_ENDIANNESS | DMA_PDEN),
|
|
LTQ_DMA_PCTRL);
|
|
break;
|
|
|
|
- case DMA_PORT_DEU:
|
|
- ltq_dma_w32((DMA_PCTRL_2W_BURST << DMA_TX_BURST_SHIFT) |
|
|
- (DMA_PCTRL_2W_BURST << DMA_RX_BURST_SHIFT),
|
|
+ default:
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ switch (rx_burst) {
|
|
+ case 8:
|
|
+ ltq_dma_w32_mask(0x0c, (DMA_PCTRL_8W_BURST << DMA_RX_BURST_SHIFT),
|
|
LTQ_DMA_PCTRL);
|
|
break;
|
|
+ case 4:
|
|
+ ltq_dma_w32_mask(0x0c, (DMA_PCTRL_4W_BURST << DMA_RX_BURST_SHIFT),
|
|
+ LTQ_DMA_PCTRL);
|
|
+ break;
|
|
+ case 2:
|
|
+ ltq_dma_w32_mask(0x0c, (DMA_PCTRL_2W_BURST << DMA_RX_BURST_SHIFT),
|
|
+ LTQ_DMA_PCTRL);
|
|
+ break;
|
|
+ default:
|
|
+ break;
|
|
+ }
|
|
|
|
+ switch (tx_burst) {
|
|
+ case 8:
|
|
+ ltq_dma_w32_mask(0x30, (DMA_PCTRL_8W_BURST << DMA_TX_BURST_SHIFT),
|
|
+ LTQ_DMA_PCTRL);
|
|
+ break;
|
|
+ case 4:
|
|
+ ltq_dma_w32_mask(0x30, (DMA_PCTRL_4W_BURST << DMA_TX_BURST_SHIFT),
|
|
+ LTQ_DMA_PCTRL);
|
|
+ break;
|
|
+ case 2:
|
|
+ ltq_dma_w32_mask(0x30, (DMA_PCTRL_2W_BURST << DMA_TX_BURST_SHIFT),
|
|
+ LTQ_DMA_PCTRL);
|
|
+ break;
|
|
default:
|
|
break;
|
|
}
|